Method for etching and/or patterning a silicon-containing layer

Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching

Reexamination Certificate

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C438S716000, C438S719000, C438S723000, C438S745000, C438S753000, C438S756000, C134S001100, C134S001200, C134S001300

Reexamination Certificate

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06890860

ABSTRACT:
Prior to etching a poly-II layer during fabrication of an integrated circuit, a hydrofluoric acid (HF) dip is used to remove surface oxides from the poly-silicon layer and an anisotropic descumming operation is used to remove any resist material left over from a patterning operation. Following patterning, a long breakthrough etch (e.g., sufficient to remove 300-1500 Å of oxide) using an anisotropic breakthrough etchant (e.g., a fluorocarbon-based etchant) is performed before the poly-silicon layer is etched. The HF dip may be repeated if a predetermined time between the first dip and the etch is exceeded. The anisotropic descumming operation may be performed using an anisotropic anti-reflective coating (ARC) etch, e.g., a Cl2/O2, HBr/O2, CF4/O2or another etch having an etch rate of approximately 3000 Å/min for approximately 10-20 seconds. The poly-silicon layer may be annealed following (but not prior to) the etch thereof.

REFERENCES:
patent: 4460435 (1984-07-01), Maa
patent: 4502915 (1985-03-01), Carter et al.
patent: 4702000 (1987-10-01), Matlock et al.
patent: 5242536 (1993-09-01), Schoenborn
patent: 5308400 (1994-05-01), Chen
patent: 5342801 (1994-08-01), Perry et al.
patent: 5346585 (1994-09-01), Doan et al.
patent: 5378648 (1995-01-01), Lin et al.
patent: 5449433 (1995-09-01), Donohoe
patent: 5453156 (1995-09-01), Cher et al.
patent: 5631178 (1997-05-01), Vogel et al.
patent: 5639681 (1997-06-01), Carmody et al.
patent: 5656533 (1997-08-01), Kim
patent: 5674354 (1997-10-01), Su et al.
patent: 5705419 (1998-01-01), Perry et al.
patent: 5792708 (1998-08-01), Zhou et al.
patent: 5811022 (1998-09-01), Savas et al.
patent: 5930650 (1999-07-01), Chung et al.
Wolf et al., Silicon Processing for the VLSI Era, 1986, vol. 1, p. 429, 446.

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