Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-06-28
2001-03-06
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S710000, C438S712000, C438S714000, C438S715000
Reexamination Certificate
active
06197698
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for etching a poly-silicon layer, and more particularly, to a method for etching a poly-silicon layer of a gate.
2. Description of the Prior Art
In semiconductor processing, the main component of the gate of the metal-oxide-semiconductor (MOS) transistor is the poly-silicon layer. After photolithography and etching are performed on the poly-silicon layer, the pattern of the gate is defined on a dielectric layer of a semiconductor wafer. In semiconductor processing with gate lengths of less than 0.18 um, ion implantation, photolithography, etching, and heat treatment are performed sequentially on the poly-silicon layer to adjust the threshold voltage of the MOS transistor. Problems arise during the etching process if the dopant-containing portion of the poly-silicon layer becomes over etched resulting in varying shapes of each gate. This lowers the reliability of semiconductor products.
Please refer to
FIG. 1
to FIG.
3
.
FIG. 1
to
FIG. 3
are schematic diagrams of the method for forming the gates
26
,
28
by using the method for etching the poly-silicon layer
14
according to the prior art. As shown in
FIG. 1
, the method for forming the gates
26
,
28
of the MOS transistor is employed in semiconductor processing with gate lengths equal to 0.18 um. First, a dielectric layer
12
and a poly-silicon layer
14
to be used as the electrode of the gate are sequentially formed on a semiconductor wafer
10
. Then, an ion implantation process is performed in a predetermined area of the poly-silicon layer
14
to implant dopants to a predetermined depth thus forming the ion implantation layer
18
. Next, an anti-reflection bottom layer
22
is formed on the poly-silicon layer
14
to decrease reflection on the surface of the semiconductor wafer
10
such that the accuracy of gate pattern transfer is not diminished. Next, a photolithography process is performed to form a plurality of photo-resist layers
24
with rectangular cross-sections in the predetermined area of the anti-reflection bottom layer
22
for defining the pattern of the gate.
As shown in
FIG. 2
, the next step involves removing the anti-reflection bottom layer
22
not covered by the photo-resist layers
24
. Then, an etching process is performed to vertically etch away the poly-silicon layer
14
and the ion implantation layer
18
not covered by the photo-resist layer
24
. As shown in
FIG. 3
, the photo-resist layer
24
is then removed thus forming the anti-reflection bottom layer
22
and the poly-silicon layer
16
in the predetermined area as a plurality of gates
26
,
28
with rectangular cross-sections.
In the method for etching the poly-silicon layer
14
according to the prior art, a combination of Cl
2
, HBr, He and O
2
is used as the etching gas. However, use of this gas combination causes the etching rate on the sidewall of the poly-silicon layer
16
to differ greatly from that on the sidewall of the ion implantation layer
18
where over etching may occur. This causes this layer to become sunken. Therefore, the sidewall of the gate
26
comprising the ion implantation layer
18
is not as vertical as the sidewall of the gate
28
without the ion implantation layer
18
, as shown in FIG.
3
. The different profiles of the gates
26
,
28
lower the reliability of semiconductor products.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a method for etching the poly-silicon layer to form the gates with the same profiles so as to enhance the reliability of semiconductor products.
In a preferred embodiment, the present invention provides a method for etching a poly-silicon layer of a semiconductor wafer, the semiconductor wafer comprising a dielectric layer, a poly-silicon layer situated on the dielectric layer and containing dopants to a predetermined depth, and a photo-resist layer having a rectangular cross-section above a predetermined area of the poly-silicon layer, the semiconductor wafer being processed in a plasma chamber, the method comprising:
performing a first dry-etching process to vertically etch away the dopant-containing portion of the poly-silicon layer not covered by the photo-resist layer; and
performing a second dry-etching process to vertically etch away the residual portion of the poly-silicon layer not covered by the photo-resist layer down to the surface of the dielectric layer;
wherein the etching gases used in the first dry-etching process differ from those used in the second dry-etching process, and the main etching gas of the first dry-etching process is C
2
F
6
.
It is an advantage of the present invention that C
2
H
6
is employed as the main etching gas in the first dry-etching process to etch away the dopant-containing portion of the poly-silicon layer so as to prevent the gate from becoming sunken. Next, the second dry-etching process can be performed to remove the residual poly-silicon layer not covered by the photo-resist layer. Therefore, the sidewalls of the gates are vertical profiles and thus the reliability of semiconductor products is increased.
This and other objective of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment which is illustrated in the various figures and drawings.
REFERENCES:
patent: 4950618 (1990-08-01), Sundaresan et al.
patent: 5468342 (1995-11-01), Nulty et al.
patent: 5627395 (1997-05-01), Witek et al.
patent: 5656533 (1997-08-01), Kim
Huang Jui-Tsen
Lin Tsu-An
Shih Kuang-Hua
Yang Chan-Lon
Hsu Winston
United Microelectronics Corp.
Utech Benjamin L.
Vinh Lan
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