Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-12-28
2004-02-17
Goudreau, George (Department: 1763)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S720000, C438S740000, C438S723000, C438S724000, C438S701000
Reexamination Certificate
active
06693042
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor device manufacturing, and more particularly, to improved methods for etching openings in intermetallic insulating layers and a semiconductor device with a thin barrier layer and well-defined contact openings.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
In the fabrication of semiconductor devices, numerous conductive device regions such as transistors, capacitors, and diodes may be formed on or above a semiconductor substrate. For example, a typical metal oxide semiconductor (MOS) transistor such as a NMOS or PMOS transistor generally includes a gate electrode formed above a substrate separated by a relatively thin gate dielectric. Conductive regions and layers of the device may be isolated from one another by an interlevel dielectric. At various stages in the fabrication of semiconductor devices, it may be necessary to form openings in an interlevel dielectric layer to allow contact to underlying regions or layers. Generally, an opening through a dielectric layer exposing a diffusion region or an opening through a dielectric layer between polysilicon and a first metal layer is called a “contact opening” or a “contact hole.” An opening in other dielectric layers such as an opening through an interlevel dielectric layer is referred to as a “via.” For purposes of this disclosure, henceforth “contact opening” may be used to refer to a contact opening and/or a via. A contact opening may expose a diffusion region within a silicon substrate such as a source or drain, or may expose some other layer or structure such as an underlying metallization layer, a local interconnect layer, or a gate structure. Conductive contact structures may be formed within the contact opening, and interconnects may overlie the contact structures and may connect neighboring contact structures.
To form such a contact opening, a masking layer having openings therethrough may be formed over the dielectric layer. In most modern processes, a dry etch may then be performed in which the wafer may be exposed to a plasma. The plasma may be formed by flowing one or more gases such as one or more halocarbons and/or one or more other halogenated compounds such as CF
4
, CHF
3
,C
4
F
8
, C
5
F
8
, C
4
F
6
(Freon 23), SF
6
, and NF
3
. In addition, gases such as O
2
, Ar, and N
2
may also be added to the gas flow. After the opening has been formed thereby exposing a portion of the region or layer to be contacted, the opening may be cleaned with a sputter etch such as a radio-frequency sputter etch. The sputter etch may be used to remove small amounts of material which may form on sidewalls or on a bottom surface of the contact opening during the dry etch process. The opening may then be filled with a conductive material so that electrical contact can be made with the underlying region or layer.
There are, however, several disadvantages to conventional methods for forming contact structures. For example, a contact opening may be etched through a dielectric layer to an underlying layer, such as a semiconductor substrate or metal interconnect layer. In this manner, an underlying layer may be exposed to the etch chemistry used to etch the dielectric. Unfortunately, an undesirable compound may be formed on the upper surface of the underlying layer when the underlying layer is exposed to the etch chemistry. For example, exposing an underlying aluminum layer to an etch chemistry which includes a fluorinated hydrocarbon may cause formation of aluminum fluoride on the upper surface of the underlying layer. Other underlying layers may also react with fluorinated hydrocarbons of an etch chemistry to form undesirable compounds. Such compounds may often be very difficult, if not impossible, to remove by conventional methods. In addition, attempts to remove such compounds may adversely affect the operation or structure of the device if, for example, damage to other dielectric or conductive features of the device is caused during removal of these compounds. Furthermore, if such compounds remain in an etched contact opening, the resistance of a contact structure formed in the opening may be adversely increased thereby causing device malfunction.
To etch a contact opening without destroying an underlying layer as described above, a barrier layer may be formed between the underlying layer and the dielectric layer. A barrier layer material may be selected such that the barrier layer does not react with the etch chemistry to form the undesirable compounds described above. A thickness of the barrier layer may depend on the etch rate of the etch chemistry. For example, depending on the rate at which the barrier layer is removed by the etch chemistry, a thickness of the barrier layer may be selected such that the barrier layer is not completely removed during the etch process. Therefore, a thickness of the barrier layer may be selected such that etching may be terminated before the underlying layer is exposed to the etch chemistry. In this manner, a contact opening may be formed through the dielectric layer without destroying the underlying layer. There are, however, several disadvantages to using such a barrier layer for forming a contact structure. For example, processing time for forming such a barrier layer may be heavily dependent upon the thickness of the barrier layer required to protect the underlying layer. In addition, due to the etch rate of typical barrier layer materials using conventional etch chemistries, the thickness of the barrier layer required to protect an underlying layer may be approximately 500 angstroms to approximately 1000 angstroms. Therefore, forming such a barrier layer may increase overall processing time, thereby reducing overall throughput and efficiency of semiconductor device manufacturing processes. Furthermore, overall cost of a semiconductor device may increase due to the expensive nature of barrier layer materials.
Although protecting the underlying layer during the process of etching a contact opening is important, forming contact openings of uniform critical uniformity across a wafer is also important. “Critical dimension”, as used in this application, may generally refer to the dimensional design value of a feature. Critical dimensions are of interest since they may represent the smallest dimension that may be formed on a semiconductor topography using various techniques such as photolithography and etch. Unfortunately, as the dimensions of advanced semiconductor devices are reduced, problems associated with forming contact openings having uniform critical dimensions across a wafer typically increase. For example, current etch processes may not form contact openings of uniform critical dimensions across a wafer. As such, the critical dimensions of the contact openings across the wafer may vary. Furthermore, the critical dimensions of contact openings may also vary from wafer to wafer.
Accordingly, it would be advantageous to develop a method for forming contact openings through a dielectric layer using a barrier layer of reduced thickness to protect underlying semiconductor or metal interconnect layers while forming contact openings of uniform critical dimension across the wafer.
SUMMARY OF THE INVENTION
The problems outlined above may be in large part addressed by a method for etching a dielectric layer formed upon a barrier layer with an etch chemistry including C
x
H
y
F
z
, in which x≧2, y≧2, and z≧2. For example, C
x
H
y
F
z
may include C
2
H
2
F
4
, which may be commonly referred to as Freon 134 or F134. In addition, C
x
H
y
F
z
may also be a heavier fluorinated hydrocarbon such as C
4
H
2
F
6
. Such an etch chemistry may be selective to the barrier layer. The selectivity of an etch chemistry or etch process may be generally defined as the ratio of the etch rates of different materials which are being etched. For example, the etch chemistry may have a dielectric layer:barrier lay
Geha Sam
Qiao Jianmin
Sedigh Mehran G.
Conley & Rose, P.C.
Cypress Semiconductor Corp.
Daffer Kevin L.
Goudreau George
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