Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-01-10
2006-01-10
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06986113
ABSTRACT:
A method for estimating noise in an integrated circuit substrate. A model file is created for a technology process for fabricating the integrated circuit. Noise generated by a digital circuit and input/output circuitry to be implemented in the integrated circuit are estimated. A substrate netlist is generated for the integrated circuit. A floorplan is determined for the integrated circuit. Transient simulations are run with predetermined input values. Finally, it is determined if predetermined noise requirements are met in results of the transient simulations.
REFERENCES:
patent: 5481484 (1996-01-01), Ogawa et al.
patent: 6291322 (2001-09-01), Clement
patent: 6553542 (2003-04-01), Ramaswamy et al.
patent: 6725185 (2004-04-01), Clement
patent: 6898769 (2005-05-01), Nassif et al.
patent: 2001/0029601 (2001-10-01), Kimura et al.
patent: 2002/0045995 (2002-04-01), Shimazaki et al.
patent: 2002/0147555 (2002-10-01), Nagata et al.
patent: 2003/0172358 (2003-09-01), Alon et al.
patent: 2003/0229874 (2003-12-01), Saito et al.
Ghosh Bipasha
Kiel Stephen N.
Sinha Snehamay
Srinivasa Raghu Nandan
Brady III W. James
Levin Naum B.
Moore J. Dennis
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