Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-10-08
2002-06-11
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06405358
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to the design of integrated circuits and in particular to the interconnect routing between blocks of an integrated circuit.
BACKGROUND OF THE INVENTION
When designing integrated circuits, top level floor planning is critical to both the speed and density of the completed circuit. Top level floor planning involves defining the size, shape, and placement location for the modules that are to be interconnected at the top level of the integrated circuit design. Often the location of signal ports for each of the modules must be defined to try to minimize the amount of routing necessary at the top level to connect all the signals. Poor floor planning may lead to signal routes that are much longer than necessary. Also, it is often possible to place the blocks in locations that make routing very difficult, if not impossible. When routing through a portion of the circuit is very difficult, many automated routers will route some signals around the congestion. This greatly lengthens the route of those signals and may significantly degrade their speed.
As integrated circuits shrink in size, routing becomes a larger factor in performance. Each signal trace has an inherent resistance and an inherent capacitance. When a signal driven from one end of a trace transitions from, for example, a high voltage to a low voltage, the received signal at the other end of the trace does not see a sharp edge, but an exponential decay in the signal voltage. This decay may be determined by calculating the time constant (&tgr;) of the circuit formed by the trace resistance and capacitance. The time constant (&tgr;) is the amount of time required for the voltage on the receiving end of the trace to decay by a factor of 1/e, where e is the base of the natural system of logarithms. 1/e is approximately equal to 0.37. This time constant (&tgr;) is calculated by multiplying the trace resistance by the trace capacitance (&tgr;=RC). Thus, these delays due to the trace are commonly called “RC delays”. As circuits shrink, these RC delays do not tend to shrink in proportion to transistor area. While the routing may shrink in physical dimensions, the capacitance may increase since the thickness of the dielectric layers is also likely to shrink. This combination may cause the contribution of RC delay to total circuit delay to increase. Therefore, the accurate modeling of RC delays becomes more critical as circuit size shrinks and transistor performance increases. These delays can only be accurately modeled when the routing distance and metal layer are known. This information is needed early in the design process so timing problems may be corrected. Early feedback to the designers of routing delays allows architectural changes before a large part of the design has been completed. This early feedback of possible problems minimizes the amount of re-work needed in the architectural change.
Many integrated circuits use routing channels between blocks to interconnect blocks without having to route over blocks. The area that these channels require is usually directly proportional to the number of signals routed in each channel. For floor planning purposes, it is necessary to fix the minimum area of each routing channel early in the design process.
Currently, many designers must perform a complete route of the integrated circuit to get even minimal routing density and RC delay information. This process is often complicated and time-consuming. Also, in many cases, if the floor plan is inadequate, the route may not complete. This leads to iterations of the floor plan in search of an adequate route.
Thus, there is a need for a method of generating estimated routing densities quickly and easily as early as possible in the design process. There is also a need for a display of these results such that the designer may quickly find the areas of the design that are most likely to have difficulty in routing given a potential floor plan.
SUMMARY OF THE INVENTION
The preferred embodiments of this invention provide a quick visual display of routing density estimates. These estimates are calculated from a proposed floor plan, and block interconnect data. By providing the designer with a fast method for estimating routing density across the integrated circuit, this invention allows very fast iterations of floor plans. These fast iterations allow the designer to choose a good floor plan for a given chip. Representative implementations of this method will typically involve the creation of a computer program to perform all of the numerous calculations required.
This process divides the area of the integrated circuit into a number of grid areas. The estimated vertical and horizontal routing densities are calculated by estimating grid areas that signals most likely will cross and summing probabilities for each of the grid areas. Both vertical and horizontal routing densities are estimated since it is possible to have a route that, in one area, is very dense with lines running vertically while very sparse in lines running horizontally. The converse is also possible, or both horizontal and vertical routing may be very dense in an area. By estimating the probability that a given signal will cross a given area in either the horizontal or vertical direction, these probabilities are summed for all the signals in the design to create and estimated routing density. The estimated routing density results may be displayed graphically on a computer display, printer, or other output device. These results include estimated vertical and horizontal routing densities for each of the areas the design has been divided into. The estimated densities for each of these areas may be displayed graphically, using shapes, shading, or color, or may be simply shown as numeric values.
From the displayed estimated densities, specific areas of the design that are likely to have routing problems during the signal routing phase of the design may be visible. The floor plan may then be modified to reduce these problem areas in an iterative manor until each of the routing problems have been mitigated.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
REFERENCES:
patent: 6067409 (2000-05-01), Scepanovic
Agilent Technologie,s Inc.
Do Thuan
Smith Matthew
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