Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2000-01-07
2001-03-20
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S585000, C438S527000, C438S918000
Reexamination Certificate
active
06204157
ABSTRACT:
TECHNICAL FIELD
The present invention relates to the fabrication of semiconductor devices, and more particularly to reducing transistor capacitances in semiconductor devices.
BACKGROUND OF THE INVENTION
Semiconductor chips or wafers are used in many applications, including as integrated circuits and as flash memory for hand held computing devices, wireless telephones, and digital cameras. Regardless of the application, it is desirable that a semiconductor chip hold as many circuits or memory cells as possible per unit area. In this way, the size, weight, and energy consumption of devices that use semiconductor chips advantageously is minimized, while nevertheless improving the memory capacity and computing power of the devices. Moreover, it is desirable that the devices operate at very fast speeds.
Among the things that can limit the speed with which semiconductor devices operate is extraneous capacitances in the devices. More specifically, undesired electrical capacitance can arise from the portions of the source and drain regions that overlap the gate region, as well as from the source and drain junctions. To minimize this undesired capacitance, the present invention understands that the thickness of the source/drain junctions preferably is minimized.
The present invention further recognizes that the junctions can be made shallow by using very low source/drain dopant implant energies and very low thermal budgets, i.e., by subsequently activating the dopant using as little thermal energy as possible. However, such techniques, while effective, are limited by current manufacturing constraints.
Another way to limit junction depth and, hence, to decrease junction capacitance is to use so-called “silicon on insulator”, or “SOI”, technology, in which a layer of oxide is buried in the silicon substrate to act as a stop to dopant diffusion (and, hence, to act as a stop to source/drain junction depth). As understood by the present invention, however, current buried oxide layers can typically be disposed in a substrate no closer than about 1000 Å to the surface of the substrate. Thus, source/drain junctions, even in SOI devices, can still be sufficiently deep to cause speed-limiting junction capacitances.
With the above shortcomings in mind, the present invention makes the critical observation that it is possible to limit the depth of the source/drain junctions in semiconductor devices (and, hence, decrease the junction capacitances) using the novel approach set forth herein.
BRIEF SUMMARY OF THE INVENTION
A method for fabricating a semiconductor device including a substrate includes establishing plural transistor gate stacks on the substrate such that at least one prospective junction region is defined in the substrate between two adjacent stacks, with the prospective junction region defining a desired lower bound. The method then includes disposing Nitrogen into the prospective junction region and annealing the substrate to cause the Nitrogen to agglomerate at a depth relative to the surface of the substrate that is greater than the desired lower bound. Dopant is next implanted into the prospective junction region, and then the substrate is annealed to activate dopant.
Preferably, the act of implanting dopant includes implanting the dopant to a depth of at least the desired lower bound. Also, the preferred method includes annealing the substrate after the act of disposing the Nitrogen and before the act of implanting the dopant. As set forth below in greater detail, a desired minimal overlap region under the gate stacks can be determined and an annealing time and temperature established for annealing the substrate with Nitrogen in response to the determining act, such that overlap capacitance is minimized. The act of annealing the substrate after Nitrogen disposition is established to cause the Nitrogen to diffuse and thereby establish the minimal overlap regions.
Other features of the present invention are disclosed or apparent in the section entitled “DETAILED DESCRIPTION OF THE INVENTION”.
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Advanced Micro Devices , Inc.
LaRiviere Grubman & Payne, LLP
Niebling John F.
Simkovic Viktor
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