Method for error reduction in lithography

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C700S121000

Reexamination Certificate

active

06883158

ABSTRACT:
The present invention relates to a method and a system for predicting and correcting geometrical errors in lithography using masks, such as large-area photomasks or reticles, and exposure stations, such as wafer steppers or projection aligners, printing the pattern of said masks on a workpiece, such as a display panel or a semi-conductor wafer. The method according to the invention comprises the steps of collecting information about a mask substrate, a mask writer, an exposure stati n, and/or about behavior of a processing step that will occur after the writing of the mask. Further the method comprises predicting from the combined information distorsions occuring in the pattern, when it is subsequently printed on the workpiece; calculating from said prediction a correction to diminish said predicted distorsion, and exposing said pattern onto said mask substrate while applying said correction for said distorsions.

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