Method for erasing memory cells in a nonvolatile memory

Details Method for erasing memory cells in a nonvolatile memory Method for erasing memory cells in a nonvolatile memory

2001-04-24

2003-01-14

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185220, C365S185290

Reexamination Certificate

active

06507522

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 2000-21646, filed on Apr. 24, 2000 and Korean Patent Application No. 2000-76373, filed on Dec. 14, 2000, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates generally to a flash memory, and more specifically to the optimization of threshold voltage distribution profiles of erased memory cells in a flash memory.
BACKGROUND OF THE INVENTION
Flash memories, including electrically erasable and programmable read only memories (EEPROMs), offer advanced performance in reading and writing (or programming) data, as compared to other kinds of nonvolatile memories. Because of its high speed operation, flash memory is the preferred memory device for portable computing devices, cellular phones, digital still cameras, and similar equipment. A typical flash memory includes a plurality of memory cells formed in a matrix of rows and columns. Erasing the memory cells is generally performed for an entire memory cell array, called a block or sector, at the same time. Programming can be conducted for one or more memory cells at a time.
FIG. 1
illustrates a conventional flash memory cell. Referring to
FIG. 1
, a conventional flash memory cell includes a floating gate transistor
10
constructed of a source
14
, a drain
16
, a floating gate
22
, and a control gate
26
. The floating gate
22
is deposited on an oxide film
20
on a channel region
18
in a bulk substrate
12
, and overlaps edges of the source
14
and drain
16
regions. The control gate
26
is formed over the floating gate
22
. An intermediate insulation layer
24
is interposed between the control gate
26
and the floating gate
22
to isolate the gate layers. This intermediate insulation layer
24
may be formed, for example, of O—N—O (oxide-nitride-oxide).
In the flash memory, the control gates
26
of each of the various transistors
10
arranged in a row are connected to the same wordline in common. Similarly, the drain regions
16
of each of the transistors
10
arranged in a column are connected to the same bitline in common. The source regions
14
of each of the transistors
10
in the flash memory are connected to a common source line in common.
A typical programming operation in a flash memory device is accomplished by inducing a hot electron injection from the channel region
18
, nearby the drain
16
, to the floating gate
22
. In order to cause the hot electron injection, the source
14
and substrate (or bulk)
12
are held at ground potential, while the control gate
26
is connected to a high positive voltage (Vg) of about 10V and the drain
16
is biased with a voltage of about 5~6V. A memory cell programmed in the manner just described has negative charges in its floating gate
22
. This, in turn, increases its threshold voltage during a read operation.
In a read operation, the drain
16
is provided with a voltage of about 1V, while the control gate
26
is connected to a power supply voltage (i.e., about 5V) and the source is connected to 0V. Since the increased threshold voltage of the programmed memory cell acts as a blocking potential on the gate voltage during a read-out operation, the programmed cell is considered to be an “off” cell. The programmed (or “off”) cell, typically has a threshold voltage of between 6V and 8V, as indicated by the Programmed State voltage distribution profile shown in FIG.
2
.
Erasing a flash memory cell is accomplished using the F-N (Fowler-Nordheim) tunneling effect. During an erasing operation, the control gate
26
is coupled to a high negative voltage of about −8V, and the substrate (or bulk)
12
is connected to a high positive voltage of about 8~10V in order to induce the tunneling therebetween. Meanwhile, the drain
16
is conditioned at a high impedance state (or a floating state). A strong electric field is induced by the difference in voltage bias conditions between the control gate
26
and bulk region
12
. This electric field causes electrons to be moved into the source
14
. F-N tunneling normally occurs when an electric field of around 6~7MV/cm is developed across the thin insulating film
20
between the floating gate
22
and bulk region
12
. The thin insulating film
20
separating the floating gate
22
and bulk region
12
typically has a thickness of less than 100 Å. The erased cell has a lower threshold voltage, typically between about 1~3V, and is therefore sensed as an “on” cell during a read operation.
In a typical flash memory cell array architecture, the bulk region (or substrate)
12
combines active regions of multiple memory cells, so that each of the memory cells formed in the same bulk region
12
are spontaneously erased at the same time. A unit of memory cells erased by a single erase operation is called a sector (or block). Sectors are configured by separating the bulk region. Each sector typically contains memory cells providing about 64K of memory.
Table 1 shows the different bias voltage levels applied to each of the various regions of a flash memory cell during the programming, erasing, and reading operation modes. In Table 1, control gate voltage is represented by Vg, drain voltage is represented by Vd, source voltage is represented by Vs, and bulk voltage is represented by Vb.
TABLE 1
Operation Mode
Vg
Vd
Vs
Vb
Programming
 10 V
5-6 V
0 V
−0.5-0 V
Erasing
 −8 V
Floating
floating
   8-10 V
Reading
5.5 V
 1 V
0 V
     0 V 
The control gate voltage Vg is supplied by a row decoder in the flash memory device. As shown in the table 1, the control gate voltage Vg varies according to the operation mode. Varying the control gate voltage Vg helps form the basic biasing conditions that establish the states of a selected memory cell. Control gate voltage Vg must be stabilized to secure reliability for the various operations.
Unfortunately, some problems exist with respect to the use of flash memories.
FIG. 2
is a graph illustrating threshold voltage distribution profiles for a Programmed State and an Erased State of a flash memory. Referring to
FIG. 2
, after a conventional erasing operation has been performed on a block of memory cells, a group of those memory cells may have threshold voltages below a minimum desired threshold voltage value (e.g., 1V) representing an erasure state. The shaded region of the Erased State voltage distribution profile indicates the number of cells in this over-erased state and the undesirably low threshold voltage region in which they lie.
Over-erased cells can result from a difference in erasing speeds between the various memory cells belonging to a sector. In general, the erasing speed depends on a coupling ratio R. The coupling ratio R is determined by a relationship between a first capacitance C
ono
, between the floating gate
22
and the control gate
26
, and a second capacitance C
tunnel
, between the floating gate
22
and channel region
18
. This ratio is determined according to the following equation:
R=C
ono
/(
C
ono
+C
tunnel
)
The first capacitance C
ono
is variable with the topology of the floating gate
22
and the thickness of the intermediate O—N—O insulation film layer
24
. The second capacitance C
tunnel
is affected by the thickness of the tunnel oxide film
20
and the width of the channel region
18
. Ensuring the uniformity of both the tunnel oxide thickness and the width of the channel region
18
is important because the second capacitance C
tunnel
has a significant effect on the coupling ratio. Providing uniformity between channel widths would significantly reduce over-erasing of the memory cells. Current manufacturing facilities, however, have been unable to sufficiently narrow or control channel width to overcome the problem of over-erasing., and uneven erasing speeds resulting in over-erased memory cells are therefore common.
The width of a threshold voltage distribution profile is called its “active width.” As c

Affiliated with

Also associated with

Rating

Method for erasing memory cells in a nonvolatile memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for erasing memory cells in a nonvolatile memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for erasing memory cells in a nonvolatile memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3070415