Method for erasing electrically erasable and programmable memory

Details Method for erasing electrically erasable and programmable memory Method for erasing electrically erasable and programmable memory

1997-05-22

1999-03-30

Nguyen, Tan T.

Static information storage and retrieval

Floating gate

Particular biasing

36518518, 36518527, G11C 1600

Patent

active

058897054

ABSTRACT:
Charges stored in a non-volatile semiconductor memory cell are erased in a manner that reduces leakage current. The cell includes source and drain regions formed on one surface of a semiconductor substrate. A channel region is defined by the source and drain regions. A tunnel oxide layer is formed over the channel region and a floating gate layer is formed on the tunnel oxide layer to store the charges. A control gate layer is formed over the floating gate. A first positive voltage is applied to the source region and a negative voltage is applied to the control gate layer. A second positive voltage is applied to the substrate. The combination of applied voltages reduces leakage current, in turn improving cell operating performance.

REFERENCES:
patent: 5349220 (1994-09-01), Hong
patent: 5438542 (1995-08-01), Atsumi et al.

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