Method for erasing and verifying nonvolatile semiconductor memor

Details Method for erasing and verifying nonvolatile semiconductor memor Method for erasing and verifying nonvolatile semiconductor memor

1994-03-03

1995-03-21

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Erase

365900, G11C 1300

Patent

active

054002877

ABSTRACT:
In a nonvolatile semiconductor memory device including nonvolatile memory cells, a predetermined number of the memory cells are simultaneously erased. Then, a verification address VADD is generated, and one of the memory cells is selected and read in accordance with the verification address. It is determined whether or not data read from a selected memory cell coincides with a predetermined value. As a result, when this data coincides with the predetermined value, the verification address is renewed, i.e., incremented or decremented, to thereby repeat a verification operation. Otherwise, the predetermined number of the memory cells are again simultaneously erased, but a verifying operation is carried out by using the same verification address.

REFERENCES:
patent: 5327384 (1994-07-01), Ninomiya

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