Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2005-03-22
2005-03-22
Anderson, Matthew D. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C365S185330
Reexamination Certificate
active
06871258
ABSTRACT:
Described herein is an erase method for an electrically erasable nonvolatile memory device, in particular an EEPROM-FLASH nonvolatile memory device, comprising a memory array formed by a plurality of memory cells arranged in rows and columns and grouped in sectors each formed by a plurality of subsectors, which are in turn formed by one or more rows. Erase of the memory array is performed by sectors and for each sector envisages applying an erase pulse to the gate terminals of all the memory cells of the sector, verifying erase of the memory cells of each subsector, and applying a further erase pulse to the gate terminals of the memory cells of only the subsectors that are not completely erased.
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Campardo Giovanni
Micheloni Rino
Scommegna Salvatrice
Anderson Matthew D.
de Guzman Dennis M.
Jorgenson Lisa K.
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
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