Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2004-01-20
2004-11-16
Phan, Trong (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185110, C365S185290
Reexamination Certificate
active
06819591
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to the field of semiconductor devices. More particularly, the present invention relates to semiconductor memory devices.
BACKGROUND ART
Memory devices are known in the art for storing electronic data in a wide variety of electronic devices and applications. A typical memory device comprises a plurality of memory cells where each memory cell defines a binary bit, i.e., either a zero (“0”) bit or a one (“1”) bit. For example, a memory cell may be defined as either being a “programmed” cell or an “erased” cell, where, according to one particular convention, a programmed cell is representative of a “0” bit, and an erased cell is representative of a “1” bit. In one type of memory cell, each memory cell stores two binary bits, a “left bit” and a “right bit.” The left bit can represent a “0” or a “1” while the right bit can represent a “0” or a “1” independent of the left bit.
Memory cells are grouped into memory sectors, where each memory sector includes a number of memory cells. During a conventional memory sector erase operation, all the bits of each memory cell within a target memory sector are pre-programmed and then subsequently erased. An over-erase correction step may also be performed after erasing all the bits of each memory cell within a target memory sector to restore one or more over-erased cells in the target memory sector to a normally-erased state, as is known in the art. However, a number of problems still remain as a result of the conventional memory sector erase operation described above. First, neighboring memory cells adjacent to edge columns of the target memory sector can become overerased. As a result, these neighboring memory cells can become a source of leakage current and can cause the memory device to improperly function or fail during read and program verify memory operations, for example. Similarly, neighboring memory cells adjacent to edge columns of redundant blocks associated with the target memory sector can also become a source of leakage current and can likewise cause the memory device to improperly function or fail during read and/or program verify operations involving target memory sector. Furthermore, any repaired blocks within the target memory sector can additionally become another source of leakage current and can also cause the memory device to improperly function or fail during read and/or program verify operations involving target memory sector. Accordingly, there exists a strong need in the art for a method for erasing a memory sector, which results in significantly reduced leakage current. There is also strong need in the art for a method for erasing a memory sector which results in a memory device with significantly reduced error and failure.
SUMMARY
The present invention is directed to a method for erasing a memory sector which results in significantly reduced leakage current. The present invention addresses and resolves the need in the art for a memory sector erase method which results in a memory device with significantly reduced error and failure. The present invention is suitable for erasing a target memory sector having a plurality of memory blocks, each of the plurality of memory blocks having a plurality of core memory cells, each of the plurality of core memory cells being capable of storing a first bit and a second bit. The target memory sector has a first edge column shared by a first neighboring memory cell. The first neighboring memory cell is capable of storing a third bit and a forth bit.
According to one exemplary embodiment, the method comprises the steps of pre-programming the first bit and the second bit of the plurality of core memory cells of the plurality of memory blocks, pre-programming one of the third bit and the fourth bit of the first neighboring memory cell, and erasing the first bit and the second bit of the plurality of memory cells of the plurality of memory blocks. The one of the third bit and the fourth bit of the first neighboring memory cell is typically adjacent to the first edge column.
According to another embodiment, the method further comprises programming the one of the third bit and the fourth bit of the first neighboring memory cell after the erasing step. In yet other embodiments, the method further comprises over-erase correcting the first bit and the second bit of the plurality of core memory cells of the plurality of memory blocks after the erasing step.
According to another embodiment, the method further comprises pre-programming the other one of the third bit and the fourth bit of the first neighboring memory cell prior to the erasing step, and programming the other one of the third bit and the fourth bit of the first neighboring memory cell after the erasing step.
With this arrangement, leakage current sources are significantly reduced during read and program verify memory operations. As a result, memory devices incorporating the method of the present invention will operate with significantly reduced error and failure. Other features and advantages of the present invention will become more readily apparent to those of ordinary skill in the art after reviewing the following detailed description and accompanying drawings.
REFERENCES:
patent: 6191976 (2001-02-01), Smayling et al.
patent: 6567303 (2003-05-01), Hamilton et al.
Chen Pau-Ling
Kurihara Kazuhiro
Shieh Ming-Huei
Yachareni Santosh
Farjami & Farjami LLP
Phan Trong
Spansion LLC
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