Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Counting – scheduling – or event timing
Reexamination Certificate
2006-10-24
2006-10-24
Barrón, Jr., Gilberto (Department: 2132)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Counting, scheduling, or event timing
C713S310000, C714S036000, C714S724000
Reexamination Certificate
active
07127630
ABSTRACT:
A method for entering test mode of an integrated circuit device is disclosed. In one embodiment of the present invention, after a lockout period, a test controller generates a signal indicating the integrated circuit is willing to enter the test mode. After the signal, the test controller monitors a test interface during a predetermined period of time for a digital password. Then, in response to a valid password being received within the predetermined period, the test controller enters the test mode. In another embodiment, in addition to the above steps, in response to the valid password being received, the test controller generates an acknowledge signal. In one embodiment, the predetermined period of time takes place during a holdoff period after the lockout period. In another embodiment, the test interface is serial.
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Barrón Jr. Gilberto
Cypress Semiconductor Corp.
Perungavoor Venkat
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