Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-07-24
2003-09-30
Ho, Hoai (Department: 2818)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06629307
ABSTRACT:
BACKGROUND OF THE INVENTION
Engineering for a typical electronic product involves printed circuit board design and manufacture. Connectors to the circuit board are individually created to accommodate interfacing to other circuit boards and signals. Often, the pins of a connector are identified by corresponding pin numbers. These printed circuit boards are verified by engineers to ensure geometry, orientation and pin number association: the geometry and orientation verifications involve the physical attributes of the circuit board and parts; the pin number verification involves manual tracing of signal pathways through the pins of the connectors and through the underlying circuit boards.
Since signal names often vary from circuit board to circuit board, and since the connections to any given board may be highly dense and complex, the verifications involving signal and pin assignments has become increasingly difficult. Errors in pin assignment, or in signal associations to pins, are easily missed in schematic reviews, particularly with the larger and larger connectors utilized with printed circuit boards. In the development of large systems of the type that include many boards, one of the most common problems involves the misconnection of signals between boards.
It is, accordingly, one object of the invention to provide methods for mapping pin assignments within printed circuit board design architectures. Other objects of the invention are apparent within the description that follows.
SUMMARY OF THE INVENTION
In one aspect, the invention provides a method for assigning pin assignments across multiple printed circuit boards of a product, including the steps of: designing a first circuit board of the product through computer aided design software; designing a second circuit board of the product through computer aided design software; forming a mapping file for one or more pin assignments of the first connector; and automatically associating pin assignments of the second connector based upon the mapping file.
In another aspect, the method may include the steps of updating design characteristics involving pin assignments of a first connector of the first printed circuit board, through the computer aided design software, and automatically updating pin assignments of the mapping file to re-associate pin assignments of a second connector of the second printed circuit board. Updates may also be made to a second connector of the second printed circuit board, with similar automatic updating re-association of pin assignments on a first connector of the first printed circuit board.
In another aspect, the mapping file is defined from inputs through a user interface coupled to one or more user stations over a network.
The method may further include the step of forming a mapping file for one or more signal connections of the first printed circuit board. The method may further include the step of automatically associating signal connections of the second printed circuit board based upon the mapping file.
In still another aspect, a system is provided for ensuring pin assignments between system board connections of printed circuit boards. A plurality of software configuration files define connections of a plurality of printed circuit boards. At least one mapping file correlates pin assignment attributes between the software configuration files. A processing section processes the configuration files and the mapping file to generate board schematics for the plurality of printed circuit boards with common pin assignment for the connections of each of the printed circuit boards.
In one aspect, a common user interface couples one or more user stations to input design information to the configuration files.
The invention is next described further in connection with preferred embodiments, and it will become apparent that various additions, subtractions, and modifications can be made by those skilled in the art without departing from the scope of the invention.
REFERENCES:
patent: 4613941 (1986-09-01), Smith et al.
patent: 5404475 (1995-04-01), Fujisono et al.
patent: 5502621 (1996-03-01), Schumacher et al.
patent: 5841664 (1998-11-01), Cai et al.
Atkinson John S
Erickson Michael John
Mantey Paul J.
Hewlett-Packard Development Company LP.
Ho Hoai
Nguyen Deo H.
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