Electrical computers and digital processing systems: processing – Processing control – Generating next microinstruction address
Reexamination Certificate
2007-01-09
2007-01-09
Zhen, Wei (Department: 2191)
Electrical computers and digital processing systems: processing
Processing control
Generating next microinstruction address
C712S233000, C703S023000, C711S140000, C717S134000, C717S135000
Reexamination Certificate
active
10022972
ABSTRACT:
The invention relates to a method to increase the visibility of effective address computation in pipelined architectures. In this method, the current effective address delay of each instruction in the pipeline is calculated. The current effective address delay is used to determine if a valid effective address is available for each instruction. If a valid effective address for an instruction is not available, it is computed if possible.
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Cipriani Christine M.
Favergeon-Borgialli Christophe
Kuzemchak Edward P.
Luley Mary P.
Brady W. James
Chow Chih-Ching
Marshall, Jr. Robert D.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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