Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – On insulating substrate or layer
Reexamination Certificate
2010-10-12
2011-11-22
Ghyka, Alexander (Department: 2812)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
On insulating substrate or layer
C438S199000, C438S478000, C257SE23145, C257SE29255
Reexamination Certificate
active
08062962
ABSTRACT:
A method for forming a semiconductor device is disclosed. The device includes a control electrode on a semiconductor P-channel layer having at least a gate dielectric layer. The gate dielectric layer has an exponentially decreasing density of defect levels Etin as function of energy from the band edges of the adjacent layer (the semiconductor P-channel layer or optionally the capping layer) toward the center of the bandgap of this layer. The method includes selecting at least one parameter of the P-channel semiconductor device such that the inversion carrier injection into the distribution of defect levels deviates from the energy level at the center of the bandgap of a layer adjacent the gate dielectric layer at the same side of the gate dielectric layer as the P-channel layer, with a value not more than about 49%, such as not more than about 40%, for example not more than about 20%, not more than about 10%, even not more than about 5% of that bandgap in eV. In one aspect, this allows reducing NBTI.
REFERENCES:
Aoulaiche et al., Negative Bias Temperature Instability on Si-passivated GE-interface, IEEE International Reliability Physics Symposium (IRPS), p. 358-362 (2008).
Franco et al., Improvements of NBTI Reliability in SiGe p-FETs, International Reliability Physics Symposium (IRPS), p. 1082-1085 (2010).
Grasser et al., A Two-Stage Model for Negative Bias Temperature Instability, International Reliability Physics Symposium (IRPS), p. 33-44 (2009).
Kaczer et al., NBTI from the perspective of defect states with widely distributed time scales, International Reliability Physics Symposium (IRPS), p. 55-60 (2009).
Kaczer et al., Ubiquitous Relaxation in BTI Stressing—New Evaluation and Insights, IEEE 46thAnnual International Reliability Physics Symposium, Phoenix, AZ p. 20-27 (2008).
Lee, et al., Demonstration of Lg˜55 nm pMOSFETs With Si/Si0.25GE0.75/Si Channels, High Ion/Ioff(>5×104), and Controlled Short Channel Effects (SCEs), IEEE Electron Device Letters, vol. 29, No. 9, p. 1017-1020, Sep. 2008.
Morshed et al., Physics-based 1/f noise model for MOSFETs with nitrided high-k gate dielectrics, Elsevier Solid-State Electronics, vol. 52, p. 711-724 (2008).
European Search Report mailed on Jan. 31, 2011 in European Patent Application No. 10186985.7.
Franco Jacopo
Kaczer Benjamin
Ghyka Alexander
IMEC
Katholieke Universiteit Leuven
Knobbe Martens Olson & Bear LLP
LandOfFree
Method for enhancing the reliability of a P-channel... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for enhancing the reliability of a P-channel..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for enhancing the reliability of a P-channel... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4312124