Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Utility Patent
1999-11-01
2001-01-02
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S763000, C438S954000
Utility Patent
active
06169041
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for enhancing the reliability of a dielectric layer of a semiconductor wafer, and more particularly, to a method for enhancing the reliability of a dielectric layer above a silicon element.
2. Description of the Prior Art
In general, one or more dielectric layers are formed between two conductors of a semiconductor wafer to provide good isolation. If there are impurities or charge carriers inside the dielectric layer, dielectric breakdown can easily occur, adversely affecting the reliability and lifetime of the semiconductor components. Consequently, each dielectric layer must be carefully fabricated to ensure the highest quality. To enhance the reliability of the dielectric layer, not only does the process for forming the dielectric layer need to be improved, but the effect of conductors adjacent to the dielectric layer, and other fabrication processes, must also be considered.
Please refer to FIG.
1
.
FIG. 1
is a cross-sectional diagram of a gate oxide
14
formed on a semiconductor wafer
10
according to the prior art. The surface of the semiconductor wafer
10
comprises a substrate layer
12
formed of single-crystal silicon, a gate oxide
14
formed of silicon oxide (SiO
2
) on a predetermined area of the surface of the semiconductor wafer
10
, and a gate
16
formed above the gate oxide
14
.
Because many unsaturated bonds are formed along the interface between the substrate layer
12
and the gate oxide
14
, impurities or oxygen ions (O
2
) (20) may diffuse upward to the surface of the substrate layer
12
. These impurities and oxygen ions can diffuse through the interface between the substrate layer
12
and the gate oxide
14
to form a trap region
18
during subsequent semiconductor processes. The trap region
18
may trap electron-hole pairs (EHP) generated in the substrate layer
12
, degrading the quality of the gate oxide
14
to such an extent that current may easily pass through it. In
FIG. 1
, circles
20
show the impurities or oxygen ions in the substrate layer
12
, and arrows
22
show the diffusion directions of the impurities or oxygen ions.
Please refer to FIG.
2
.
FIG. 2
is a cross-sectional diagram of a dielectric layer
38
formed within a capacitor
34
on a semiconductor wafer
30
according to the prior art. The capacitor
34
is formed in a predetermined area on the surface of the semiconductor wafer
30
. The capacitor
34
comprises a storage node
36
formed of poly-silicon, a dielectric layer
38
formed of an ONO (oxide-nitride-oxide) complex structure, and an upper field plate
40
formed of poly-silicon.
The poly-silicon layer of the storage node
36
is formed of a large number of single crystal silicon grains with different crystal orientations. Neighboring silicon grains with different crystal orientations form a grain boundary between them. Each grain boundary connects to another to form a mesh-like structure. Charge carriers move easily along the particular directions of the grain boundaries. As a consequence of this, when a current enters the storage node
36
, the current converges in some areas between the dielectric layer
38
and the storage node
36
. The current density may be so high in these areas that the crystalline structure of the dielectric layer
38
can be damaged, negatively impacting the lifetime of the dielectric layer
38
and the reliability of the capacitor
34
. In
FIG. 2
, arrows
42
show the direction of current in the semiconductor wafer
30
, and arrows
44
show the various directions of current in the storage node
36
.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a method for enhancing the reliability of a dielectric layer of a semiconductor wafer to prevent impurities, oxygen ions and currents from converging at the surface of the silicon element below the dielectric layer so as to solve the above mentioned problems.
In a preferred embodiment, the present invention provides a method for enhancing the reliability of a dielectric layer of a semiconductor wafer. The surface of the semiconductor wafer comprises a substrate layer. The method comprises
performing an ion implantation process on the surface of the semiconductor wafer to implant argon ions with a dosage around 10
15
~10
16
ions/cm
3
and an energy around 3~50 KeV into a region for a thickness of 500 Å to form an ion implantation layer; and
forming a gate oxide formed of silicon oxide on a predetermined area of the region;
wherein the ion implantation layer is used to prevent oxygen ions (O
2
−
) and impurities from diffusing upward from the substrate layer so as to enhance the reliability of the gate oxide.
It is an advantage of the present invention that the method uses argon ions to form a barrier layer so that the dielectric layer is shielded from oxygen ions and impurities, thereby enhancing the reliability of the dielectric layer.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment which is illustrated in the various figures and drawings.
REFERENCES:
patent: 4818711 (1989-04-01), Choksi et al.
Chen Chun-Huang
Liu Tien-Jui
Ghyka Alexander G.
Hsu Winston
Niebling John F.
United Microelectronics Corp.
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