Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-04-17
2002-12-17
Quach, T. N. (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S705000, C438S798000
Reexamination Certificate
active
06495455
ABSTRACT:
TECHNICAL FIELD
This invention relates to a method for enhancing selectivity between a film of a light-sensitive material and a layer to be subjected to etching in the course of electronic semiconductor device fabrication processes.
BACKGROUND OF THE INVENTION
As is well known, the fabrication of electronic semiconductor devices involves subjecting wafers of a silicon semiconductor to a number of chemio-physical treatments in order to define complex patterns of monolithically integrated electronic circuits thereon.
Specifically for defining submicron geometries, a processing technique known as plasma etching is used extensively whereby thin films of both conductive and dielectric materials can be etched.
For example,
FIG. 1
a
shows schematically a portion of a semiconductor substrate
1
on which has been deposited a layer or film
2
of a suitable material for plasma etching, which film may be a dielectric layer, a layer of polycrystalline silicon, or a metallization layer.
FIG. 1
b
shows schematically the same semiconductor portion as overlaid with a layer
3
of a light-sensitive material, e.g., a photoresist.
As is well known, to define patterns in the underlying layer
2
, the photoresist must be subjected to a photolithographic process for hardening predetermined portions
4
of the photoresist. A subsequent flushing step will result in the uncured photoresist portions being removed to leave the portions
4
as masks for corresponding portions of the layer
2
underneath, as shown in
FIG. 1
c.
At this point, a selective plasma etching step allows the patterns defined in the photoresist layer
3
to be transferred onto the layer
2
. The masks represented by the cured photoresist portions
4
will protect the layer
2
during the etching step, as shown in
FIG. 1
d.
Finally, the photoresist masks are removed to reveal the structure shown in
FIG. 1
e.
One of the most important features of plasma etch processing is etch selectivity between the photoresist and the layer
2
to be etched. Briefly stated, the etching rate ratio of the two layers is vital to a successful etching operation.
The problems involved in providing for a high etch selectivity are discussed in U.S. Pat. No. 5,277,757, for example.
The selectivity values to be obtained by current technologies usually lie within the range of 2 to 15.
With too low a selectivity, the photoresist may become exhausted before the layer
2
being processed is fully etched. Thus, if the etching were continued, the upper portion of the layer
2
would no longer be protected by the photoresist, and would be etched itself. The outcome of this is an unacceptable degradation of the patterns, leading to possible losses in the yield of approved devices for operation.
To clarify the above points, attention is directed to
FIGS. 2
a
and
2
b
, which reproduce photographs taken at an electron microscope of two identical profiles of aluminum metal interconnects.
FIG. 2
a
shows a profile wherein etch selectivity has been adequate to ensure that the etched layer could take a desired shape with a rectangular cross-section.
Conversely,
FIG. 2
b
shows a profile wherein etch selectivity has been inadequate to provide the desired shape for the etched layer; in fact, a degradation of the top surface is clearly noticeable.
With the current trend of integrated circuit fabrication technology towards defining ever smaller geometric structures, which involves lithographic constraints in terms of focal depth (Deep UV), it becomes necessary to use photoresist layers of ever smaller thickness.
Such thin layers are inherently less resistant to etching processes, and result in even lower selectivity.
In summary, there exists a growing demand for new technologies effective to enhance selectivity during etching processes.
A prior attempt at filling this demand has been a technology known as “photostabilization”. It provides for exposure of the semiconductor material wafers to high-intensity UV radiation at an elevated temperature, about 200° C.
This treatment is described in a publication “The Platform for Excellence for Photoresist Processing”, GEMINI, and is carried out after the layer
2
to be etched has been deposited and the photoresist patterned for plasma etching. Accordingly, the wafer
1
would be photostabilized after the step of
FIG. 1
c
and ahead of the step of
FIG. 1
d.
Photostabilization causes the characteristics of the resin comprising the photoresist to undergo modification, and produces cross-linking reactions between the polymer chains. This provides increased resistance to plasma etch processing.
While being advantageous in more than one way, this prior technique concurrently causes the photoresist to become more dense, which if carried too far can result in the post-etch dimensions being excessively small and unacceptable. This same problem has also been encountered where a photoresist of the Deep UV type was used.
In addition, the photostabilization technique requires the availability of special equipment.
A second prior technique consists of radiating the wafer with an electron beam. This technique is described, for example, by M. Ross et al. in a publication “Characterization of Electron Beam Stabilization of Deep-UV Resist”, Proceedings of the Microlithography Seminar INTERFACE 1997, page 119.
This radiation step is also carried out after the step of
FIG. 1
c
and before the step of
FIG. 1
d.
An electron source is used for the purpose, with the electrons being accelerated towards the wafer surface by means of an electron gun.
The last-mentioned technique has the same advantages and the same drawbacks as that previously discussed.
A further approach is described in Japanese Patent Specification No. JP-01 288853, which relates to a semiconductor wafer processing technique using a reactive gas, such as CF
4
.
In this way, an additional barrier layer is created over the photoresist.
SUMMARY OF THE INVENTION
An embodiment of the present invention provides a method for enhancing selectivity between a film of a light-sensitive material and a layer to be etched in processes for fabricating electronic semiconductor devices. The method has such functional features as to effectively improve selectivity without introducing additional steps in the process.
The embodiment provides a method as above which can be implemented without the use of special equipment.
In one embodiment, the method radiates the wafer of semiconductor material with an ion beam.
Another embodiment provides for the wafer of semiconductor material to be exposed to a chemically inert plasma medium, that is a medium comprising non-reactive noble gases.
The features and advantages of the invention will be apparent from the following description of an exemplary, though not limitative, embodiment thereof illustrated by the accompanying drawings.
REFERENCES:
patent: 4068018 (1978-01-01), Hashimoto et al.
patent: 4468284 (1984-08-01), Nelson
patent: 5679499 (1997-10-01), Yamamori
patent: 5858879 (1999-01-01), Chao et al.
patent: 5994225 (1999-11-01), Liu et al.
patent: 6121154 (2000-09-01), Haselden et al.
patent: 6271154 (2001-08-01), Shen et al.
Alba Simone
Vassalli Omar
Quach T. N.
SEED IP Law Group PLLC
STMicroelectronics S.r.l.
Tarleton E. Russell
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