Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-01-16
2004-09-21
Nguyen, Cuong (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S306000
Reexamination Certificate
active
06794704
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to semiconductor devices, and more particularly to semiconductor capacitor constructions and methods of forming semiconductor capacitors, particularly in applications for forming dynamic random access memory (DRAM) cell structures and integrated circuitry incorporating DRAM cell structures.
BACKGROUND OF THE INVENTION
The continuing densification and miniaturization of integrated circuits has led to smaller areas that are available for semiconductor memory devices. For example, in the fabrication of high density dynamic random access memory cells (DRAMs), there is less area available for the storage node (capacitor) of a memory cell. However, the capacitor must have a minimum storage capacitance to ensure operation of the memory cell. There is also a need for increased storage to enable devices to perform more functions at a faster rate.
Several techniques have been developed to increase the storage area of the capacitor within a limited space. For example, surface area has been increased by forming the capacitor in a trench or as a stacked structure. The surface area of the capacitor has also been achieved by increasing the surface roughness of the lower electrode that forms the storage node.
One prior art process for increasing the electrode surface area by forming a rough upper surface is illustrated in
FIGS. 1A-1D
, with respect to forming the lower electrode as a layer of hemispherical grain (HSG) polysilicon. Referring to
FIG. 1A
, a semiconductor wafer fragment
10
is shown in a preliminary processing step to form a DRAM capacitor. Wafer fragment
10
comprises a semiconductor material
12
(e.g., monocrystalline silicon) and wordlines
14
,
16
, having nitride spacers
18
formed laterally adjacent thereto. A diffusion region
20
within the substrate material
12
is positioned between wordlines
14
,
16
, and electrically connected by the transistor gates that are comprised by wordlines
14
,
16
. An insulative layer
22
such as borophosphosilicate glass (BPSG) has been formed over the semiconductive material
12
and the wordlines
14
,
16
. A doped polycrystalline plug
24
has been formed through the insulative layer
22
to provide electrical contact between the capacitor and a diffusion region
20
between wordlines
14
,
16
. A contact opening
26
has been formed through the insulative layer
22
to the plug
24
. A thin, heavily doped and substantially amorphous or pseudo-crystalline silicon layer
28
has been deposited over the insulative layer
22
and plug
24
.
Referring to
FIG. 1B
, according to the prior art process, an undoped amorphous or pseudo-crystalline silicon layer
30
is deposited over the doped amorphous or pseudo-crystalline silicon layer
28
. The wafer fragment
10
is then exposed to a silicon source gas such as silane or disilane (arrows
32
) to form a seed layer of silicon crystals or nucleation centers that are introduced into and distributed over the surface of the undoped amorphous or pseudo-crystalline silicon layer
30
, as shown in
FIG. 1C
, to facilitate subsequent hemispherical grain growth. The wafer fragment
10
is then thermally annealed to convert the undoped amorphous or pseudo-crystalline silicon layer
30
into crystalline structures that are facilitated by the randomly distributed silicon crystals of the seed layer. The thermal treatment causes the polycrystalline silicon to agglomerate around the seed crystals and form HSG polysilicon
34
, resulting in the storage node structure
36
shown in FIG.
1
D. Although not shown, the DRAM cell is then completed by forming a thin cell dielectric layer over the structure, followed by the formation of a second cell plate (i.e., top electrode), typically a conductively doped polysilicon or metal-based layer.
Although the HSG polysilicon increases the surface area of the lower capacitor electrode, current HSG-type methods for increasing capacitor surface area are approaching physical limitations. A disadvantage of using HSG silicon to form a container type capacitor structure) is that morphology needed to increase surface area is a function of inexact physical conversion of conductive films. HSG silicon morphology required to gain surface area enhancements needed for next generation part types borders on over-consumed, bulbous grain formations that are structurally unsound. Current technology does not allow ordered HSG silicon formation, and unwanted patterns from temperature gradients across the wafer and from gas flow dynamics create large variability in surface area enhancement. Inexact ordering and size of converted grains can be problematic. For example, the grains of the silicon overgrow and form discontinuous and isolated islands. Further, if HSG silicon growth is too extensive and extends to the opposing sides of the container, the surface area of the capacitor plate decreases. In addition, since seeding is not instantaneous and takes a finite and prolonged amount of time, grains formed at the beginning of seeding are larger than grains formed from seeds deposited at the end of the seeding step. It would be desirable to have more precise and uniform roughness provided over the surface of the capacitor plate to increase surface area.
SUMMARY OF THE INVENTION
The present invention relates generally to semiconductor fabrication techniques and, more particularly, to the formation of a capacitor electrode.
In one aspect, the invention provides methods of forming a lower electrode structure in a capacitor of a semiconductor device. In one embodiment of the method, a texturizing layer in the form of a nanorelief or nanoporous film is formed prior to deposition of the cell conductive layer to form the lower electrode. The texturizing layer can comprise an ordered array of nanostructures and/or periodic network of surface structures having substantially uniform dimensions (e.g., height, size).
In another embodiment of the method, a polymeric material is deposited over the insulative layer of a container as a precursor that is converted to relief or porous structures upon ozonolysis and UV exposure, resulting in a textured layer comprising an insulative silicon oxycarbide film. The polymeric material comprises a hydrocarbon block and a silicon-containing block. The volume fraction of the hydrocarbon block relative to the silicon-containing block can be varied to form the nanostructures as a relief structure or a porous structure. The film is punch-etched (e.g., RIE) to clear an opening to the underlying substrate or conductive plug at the bottom of the cell for the subsequent deposition of a conductive material (e.g., polysilicon, conductive metal), resulting in a lower electrode have an upper roughened surface. After formation of the lower capacitor electrode, the structure is further processed to complete the capacitor by depositing a dielectric layer and forming an upper capacitor electrode over the dielectric layer. The capacitor can usefully be integrated into a DRAM cell.
In another embodiment of a method of the invention, a texturizing underlayer is fabricated from a conductive material prior to depositing a conductive layer to form the lower electrode. In forming the texturizing underlayer, a first conductive metal is deposited over the insulative layer of a container, a second dissimilar conductive metal is deposited over the first metal layer, and the two metal layers are annealed resulting in a textured layer comprising surface dislocations in a strain relief pattern, which is preferably a periodic and ordered array of nanostructures. A conductive metal is then deposited in gas phase over the texturizing layer whereby the depositing metal agglomerates onto the surface dislocations forming island clusters. Preferably, the surface dislocations of the texturizing layer are formed as a periodic network, and the overlying conductive layer comprises ordered arrays of metal island clusters. The capacitor can then be completed by depositing a dielectric layer and forming an upper capacitor electrode over the di
Hofmann James J.
Mercaldi Garry A.
Yates Donald L.
Micro)n Technology, Inc.
Nguyen Cuong
Whyte Hirschboeck Dudek SC
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