Electrical computers and digital processing systems: virtual mac – Task management or control – Process scheduling
Reexamination Certificate
2007-10-17
2009-06-02
Bullock, Jr., Lewis A (Department: 2195)
Electrical computers and digital processing systems: virtual mac
Task management or control
Process scheduling
C718S104000
Reexamination Certificate
active
07543295
ABSTRACT:
A system of the present invention includes: a memory device which includes a first memory area for storing first information indicating that a first task acquires or attempts to acquire a lock, and a second memory area for storing second information indicating that a second task acquires or attempts to acquire the lock, and in which a time lag may occur between a time when the first task issues a writing instruction and a time when the written content is enabled to be referred to by the second task; a first acquisition section which reads the second memory area after issuing a writing instruction to write the first information to the first memory area in response to a request from the first task, and which makes a reply indicating a success of the lock acquisition on condition that the second information is not read; and a second acquisition section which writes the second information to the second memory area in response to a request from the second task, which enables the written content to be referred to by the first task, which thereafter executes a write-reflection process for enabling the content written in the first memory area by the first task to be referred to by the second task, which reads the first memory area after completion of the write-reflection process, and which makes a reply indicating a success of the lock acquisition on condition that the first information is not read from the first memory area.
REFERENCES:
patent: 5352397 (1994-10-01), Hara et al.
patent: 2003/0041225 (2003-02-01), Mattina et al.
patent: 2007/0094669 (2007-04-01), Rector et al.
patent: 1310466 (1989-12-01), None
patent: 5064825 (1993-03-01), None
patent: 10254769 (1998-09-01), None
patent: 2002175287 (2002-06-01), None
Johnson Graeme
Kawachiya Kiyokuni
Koseki Akira
Onodera Tamiya
Bullock, Jr. Lewis A
International Business Machines - Corporation
Shimokaji & Associates P.C.
Truong Camquy
Yaghmour Rosa S.
LandOfFree
Method for enhancing efficiency in mutual exclusion does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for enhancing efficiency in mutual exclusion, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for enhancing efficiency in mutual exclusion will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4072653