Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-08-08
2003-07-22
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06598216
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to integrated circuit designs in general, and in particular to application specific integrated circuit (ASIC) designs. Still more particularly, the present invention relates to a method for enhancing a power bus in input/output regions of an ASIC device.
2. Description of the Related Art
Generally speaking, there are two types of integrated circuit (IC) devices according to the types of market to which they are sold. The first type of IC devices is referred to as commodity IC devices and the second type of IC devices is referred to as application specific IC (ASIC) devices. Because commodity IC devices, such as dynamic random access memories, can be sold in vast quantities to a large number of customers, dedicated mask sets are typically employed to fabricate commodity IC devices. The relatively large one-time or non-recurring engineering costs associated with the design and layout of dedicated mask sets can typically be justified by the extremely large number of units over which the non-recurring costs can be distributed.
In contrast, ASIC devices refer to, as the name implies, devices that are customized for the needs of a particular application or a particular customer. Because of the inherently limited market associated with ASIC devices, non-recurring engineering costs have a more dramatic impact on the per-unit cost for each ASIC device. In order to keep the non-recurring costs low, ASIC design methodology is highly structured and highly dependent upon reuse of building block components in order to be cost and resource efficient. Templates for top-level chip power bus and chip-to-package interconnect are one example of building block component reuses. Top-level chip power templates typically define the size of a chip, locations of all interconnect points between the chip and its package, the layout of the power bus system for the chip, and the physical area where input/output (I/O) circuits can be placed on the chip. Most ASIC libraries have a standard set of templates, which includes top-level chip power templates, that are expected to be used on the majority of customer designs. A template is chosen by an ASIC designer based on quantity of logic, number of I/O circuits, expected power dissipation, and performance requirements. The template decision is made no later than when the technology dependent gate level description of a logic model needs to be combined with the I/O circuit placement information for floor planning and timing. From an ASIC designer's point of view, the optimal I/O placement is where there is a short, direct path between the I/O circuit and the logic connected to the I/O circuit. Unfortunately, the ASIC designer must also consider the I/O supply voltages needed, I/O power requirements, power bus, electromigration and I/O noise issues. These constraints often provide difficulties for the ASIC designer to place I/O circuits in an optimal fashion.
For example, current ASIC technologies provide the ability to have a secondary power supply voltage, in addition to a primary power supply voltage, in the I/O area of a peripheral footprint chip. Such ability allows an ASIC designer the flexibility of using industry standard I/O circuits that require a supply voltage other than the primary internal logic voltage. In order to provide such dual power bus flexibility, the power bus metal widths have to be limited to support double power buses within a fixed amount of silicon area. The result is reduced current carrying capability on each of the two power buses. This is not a problem when most ASIC designers are assumed to use both the primary and the secondary I/O power supply voltages that split the current amount required from those two power buses. However, there are many situations when the ASIC designer uses I/O circuits that only require the primary supply voltage. In those situations, it may be necessary to electrically enhance the primary supply bus in order to meet the I/O current demands. Consequently, it would be desirable to provide a method for enhancing a power bus in ASIC designs without incurring the cost of chip template customization.
SUMMARY OF THE INVENTION
In accordance with a preferred embodiment of the present invention, an I/O assignment for I/O circuits to be utilized in an ASIC design is initially generated. Each I/O circuit may obtain power from either a primary I/O power bus or a secondary I/O power bus. A determination is then made as to whether or not the I/O assignment meets certain predetermined power distribution requirements. If a group of I/O circuits only uses the primary power supply and there is a determination that the I/O assignment of this group of I/O circuit does not meet the predetermined power bus distribution requirements, a power enhancement circuit is added. The power enhancement circuit includes at least one metal line for connecting the primary I/O power bus to the secondary I/O power bus in order for the I/O assignment to meet the power bus distribution requirements.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.
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Chan Francis
Chiu Charles S.
Cusimano Robert Charles
Kent Donald S.
Yasar Gulsun
Bracewell & Patterson L.L.P.
Henkler Richard A.
International Business Machines - Corporation
Kik Phallaka
Smith Matthew
LandOfFree
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