Method for engineering the threshold voltage of a device...

Details Method for engineering the threshold voltage of a device... Method for engineering the threshold voltage of a device...

2001-05-31

2002-12-03

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Introduction of conductivity modifying dopant into...

Ion implantation of dopant into semiconductor region

C438S217000

Reexamination Certificate

active

06489224

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to transistor devices and, more particularly, to low power and ultra-low power transistor devices.
BACKGROUND OF THE INVENTION
In modern computer systems, power density and scalability issues represent some of the most significant obstacles to increased system performance. For reliability, the supply voltage Vdd must come down. In addition, to control leakage current, the threshold voltage must come up. Consequently, performance is being rapidly squeezed between the two. In addition, with an electronics market that stresses portability, compact size, lightweight and the capability for prolonged remote operation, a demand has arisen for low power and ultra-low power transistor devices and systems. To meet this demand devices are emerging which have extremely low threshold voltages.
In the prior art, devices were introduced that included buried wells. Typically these buried wells were N-type buried wells that were used for connecting N-wells surrounding PFET devices.
FIG. 1A
illustrates a prior art structure
100
. Prior art structure
100
included a P-type substrate
101
. A first NFET
105
was formed in P-type substrate
101
and included N-type source
106
, N-type drain
108
, gate electrode
107
, and active region
109
. P-type substrate
101
also included a first N-well
119
with first PFET
115
formed in it. First PFET
115
included P-type source
116
, P-type drain
118
and gate electrode
117
. A second NFET
125
including N-type source
126
, N-type drain
128
and gate electrode
127
was also formed in P-type substrate
101
. In addition, a second PFET
135
was formed in second N-well
139
and included P-type source
136
, P-type drain
138
and gate electrode
137
. Prior art structure
100
also included buried N-type well
103
, or buried N-well
103
, that was positioned below transistors
105
,
115
,
125
and
135
and connected N-wells
119
and
139
of PFETs
115
and
135
.
According to the prior art, the sole purpose of buried N-well
103
was to connect N-type wells
119
and
139
of PFETs
115
and
135
with other N-type wells (not shown) and other PFETs (not shown) that were formed in prior art structure
100
. For a more detailed discussion of prior art buried wells and their structures and purpose, see the related Patents listed below, all of which list the inventor of the present invention and are assigned to the assignee of the present invention, and are incorporated herein, in their entirety, by reference.
As noted above, according to the teachings of the prior art, buried N-well
103
was used strictly to interconnect N-wells
119
and
139
of PFETs
115
and
135
. Consequently, in the prior art, it was specifically taught to minimize and, if possible, eliminate all electrical interaction of buried N-well
103
with transistors
105
,
115
,
125
, and
135
. In the prior art, a great deal of energy and thought was devoted to this goal and it was taught that, ideally, there should be no interaction between buried N-well
103
and any of the transistors. In other words, in the prior art, N-well
103
was not considered an element, or a factor, in engineering the operation or threshold voltage of transistors
105
,
115
,
125
and
135
. To this end, in the prior art, great care was taken to use the correct energies and dopant concentrations in forming buried N-well
103
to try to obtain an ideal dopant concentration distribution for buried N-well
103
.
FIG. 1B
shows NFET
105
of
FIG. 1A
in detail along with a graph of the dopant concentration, along horizontal axis
151
, versus the depth below surface
110
of NFET
105
, along vertical axis
153
.
FIG. 1B
shows an idealized curve
150
of the prior art ideal dopant concentration distribution for NFET
105
. As seen in
FIG. 1B
, in the prior art, ideally, there was no dopant in region
155
of curve
150
, i.e., the dopant concentration was ideally zero until the first surface
102
of buried N-well
103
. Then at depth
152
, corresponding to the depth of first surface
102
of buried N-well
103
, there would ideally be an immediate increase in dopant concentration to form pulse
158
. In the prior art, it was taught that, ideally, the dopant concentration would remain high through region
157
until depth
154
, the depth corresponding to the depth of second surface
104
of buried N-well
103
, was reached. According to the prior art, ideally, the dopant concentration would then immediately drop back to zero at second surface
104
of buried N-well
103
, and remain at zero throughout portion
159
of curve
150
.
As noted above,
FIG. 1B
represents an ideal dopant concentration distribution as taught by the prior art. However, in actual practice, this ideal dopant concentration distribution was not obtainable and, in reality, the dopant concentration was more of a Gaussian distribution centered on the centerline of buried N-well
103
.
FIG. 1C
shows NFET
105
of FIG.
1
A and
FIG. 1B
in detail along with a more realistic graph of the dopant concentration, along horizontal axis
151
, versus the depth below surface
110
of NFET
105
, along vertical axis
153
.
FIG. 1C
shows a realistic curve
150
R of the dopant concentration distribution for NFET
105
. As seen in
FIG. 1C
, there is a small dopant concentration in region
155
of curve
150
R, i.e., a dopant concentration tail exists in region
155
. This small dopant concentration in region
155
of curve
150
R typically increases with depth throughout region
155
, and the first half of region
157
, of curve
150
R, through and past the first surface
102
of buried N-well
103
, to the depth of centerline
103
C of buried N-well
103
. The dopant concentration then typically reaches a peak
158
R at a depth approximately equal to the depth of centerline
103
C of buried N-well
103
. After peak
158
R, the dopant concentration typically decreases with depth along curve
150
R through the second half of region
157
, and all of region
159
, i.e., a dopant concentration tail exists in region
159
.
As noted above, the Gaussian distribution of
FIG. 1C
was considered problematic in the prior art and considerable energy was spent trying to obtain a dopant concentration distribution closer to the graph of
FIG. 1B
than that of FIG.
1
C. This was because, as discussed above, in the prior art, it was thought that ideally, there should be no interaction between buried N-well
103
and NFET
105
.
What is needed is a method and structure that operates well under realistic conditions. In addition, a method and structure is highly desirable that uses the non-ideal dopant concentration, and dopant concentration tail, as a tool for engineering the threshold voltage of the transistor.
SUMMARY OF THE INVENTION
In contrast to the structures and teachings of the prior art, the present invention includes a method and structure for using buried platform wells specifically to electrically interact with the platform transistors of the invention. According to the invention, the dopant concentration distribution of the buried platform wells is used to change the threshold voltage of the platform transistors of the invention by introducing a tail dopant concentration into the active region of the platform transistors.
Further, according to the invention, the tail dopant concentration distribution can be engineered to yield a desired threshold voltage for the platform transistor and this threshold voltage can be varied from transistor to transistor. Consequently, according to the method and structure of the invention, the Gaussian dopant concentration distribution that was avoided, minimized, and considered undesirable, in the prior art, is used as an advantageous integral element of the platform transistors of the invention.
The platform transistors of the invention can also be used in conjunction with standard transistors, on a single structure, to provide both low and relatively high threshold voltage transistors on a single structure. As a result of the

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