Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-10-09
2004-08-24
Nguyen, Ha Tran (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S612000, C438S614000, C438S745000, C438S749000, C438S751000, C438S754000
Reexamination Certificate
active
06780751
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to solder joints and to methods for forming the same, and relates more particularly to methods for preparing an under bump metallization layer for solder plating and reflow.
BACKGROUND OF THE INVENTION
The use of solder bumps in attaching die to flip-chip packaging is well known in the art. FIG.
1
and
FIG. 2
(the later of which is a magnified view of REGION
2
of
FIG. 1
) illustrate one type of prior art solder joint
10
that is used in flip chip applications. As shown therein, a die
11
is provided which has an I/O pad or die pad
13
disposed thereon. A photo polymer passivation layer
17
is provided to protect the die from damage. A seed metallization
14
is disposed on the die pad, and an Under Bump Metallization (UBM) layer
15
is disposed on the seed metallization. A solder ball
19
is then placed or formed on top of the UBM structure and is bonded to the underlying UBM through reflow (that is, by heating the solder composition sufficiently so that it liquefies). The solder ball is used to form an electrical and mechanical connection between the die and a Printed Circuit Board (PCB)
21
or other device.
There is currently a movement in the art to replace tin-lead solders that have been widely used in die attach operations with lead-free solders, due to the health and environmental problems that lead-based solders pose. Indeed, the National Electronics Manufacturing Initiative (NEMI) has formally endorsed the use of certain lead-free solders, and in particular, tin-based lead-free solders, for various applications. Thus, for example, NEMI has advocated the use of SnAg
3 9
Cu
0.6
in solder reflow operations used in conjunction with most of the PC boards produced today, and is also recommending two other lead-free alloys, SnCu
0 7
and SnAg
3 5
, for wave soldering applications.
However, while these tin-based solders have a number of advantageous properties, they also suffer from some infirmities. In particular, solder joints based on these materials are often found to have lifetimes that are significantly shorter than projected lifetimes based on theoretical considerations. In other words, the incidence of solder joint failure per unit time for solder joints based on these materials is often found to be unexpectedly high.
There is thus a need in the art for improved solder joints based on lead-free solders (particularly lead-free tin-based solders) that exhibit longer lifetimes. There is also a need in the art for a method for achieving such solder joints. These and other needs are met by the methodologies described herein.
SUMMARY OF THE INVENTION
In one aspect, a method for plating solder onto a die is provided. The method is particularly useful with lead-free solders, such as SnCu, SnAg and SnAgCu. In accordance with the method, a die is provided which has a seed metallization thereon. The seed metallization preferably comprises a first layer of TiW and a second layer of copper, and also preferably has a photoresist disposed thereon which has been patterned to create at least one aperture through which a portion of the seed metallization is exposed. The exposed seed metallization is etched with a (preferably dilute, aqueous) solution comprising an acid (such as, for example, sulfuric acid) and an oxidizer (such as, for example, sodium persulfate), thereby forming an etched seed metallization. An under bump metallization (UBM) which preferably comprises copper is then electroplated onto the etched seed metallization. The wafer is then preferably rinsed with deionized water, and a solder composition (preferably lead-free) is electroplated onto the UBM.
In another aspect, a method for etching a UBM is provided. In accordance with the method, a die is provided having a seed metallization, a UBM disposed on the seed metallization, and a lead-free solder composition disposed on the UBM. The seed metallization is then etched and possibly rinsed, and the UBM is etched with a solution comprising an acid and an oxidizer. A solder flux is then dispensed onto the die, and the solder composition is reflowed.
In still another aspect, a method for plating solder on a die is provided. In accordance with the method, a die is provided which has a die pad disposed thereon. A seed metallization is formed over the die pad, and a photo-definable polymer is disposed over the seed metallization. The photo-definable polymer is then patterned and exposed to create an aperture which exposes at least a portion of the seed metallization, after which the exposed portion of the seed metallization is etched with a solution comprising an acid and an oxidizer. A UBM, which preferably comprises copper, is then electroplated onto the etched portion of the seed metallization, and a (preferably lead-free) solder composition is electroplated onto the UBM.
In still another aspect, a method for electroplating a solder composition is provided. In accordance with the method, a substrate is provided which has a seed metallization disposed thereon. The seed metallization is then etched with a solution comprising an acid and an oxidizer, and a copper UBM is electroplated onto the seed metallization.
These and other aspects of the present disclosure are described in greater detail below.
REFERENCES:
patent: 4950623 (1990-08-01), Dishon
patent: 5162257 (1992-11-01), Yung
patent: 6251501 (2001-06-01), Higdon et al.
patent: 6293457 (2001-09-01), Srivastava et al.
patent: 6555459 (2003-04-01), Tokushige et al.
Chemelex Product Data Sheet, Circutek ME-600, RBP Chemical Technology, Milwaukee, WI, Feb. 15, 2002, 2 pages.
“Lead Free Electronics Assembly: How Will This Unfold?,” Prismark Partners LLC, May 2002, pp. 1-12.
“Implementing Cleaner Printed Wiring Board Technologies: Surface Finishes,” Design for the Environment Printed Wiring Board Project, U.S. Environmental Protection Agency, Mar. 2000, pp. 1-41.
Fortkort John A.
Freescale Semiconductor Inc.
Hulsey Grether & Fortkort LLP
Nguyen Ha Tran
LandOfFree
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