Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2000-02-15
2001-04-24
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S436000, C438S437000, C438S424000, C438S425000
Reexamination Certificate
active
06221735
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor devices and their fabrication and, more particularly, to reducing stress-induced dislocations in semiconductor devices and improving their performance.
BACKGROUND OF THE INVENTION
The electronics industry continues to rely upon advances in semiconductor technology to realize higher-functioning devices in more compact areas. For many applications, realizing higher-functioning devices requires integrating a large number of electronic devices into a single silicon wafer. As the number of electronic devices per given area of the silicon wafer increases, the manufacturing process becomes more difficult.
A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. Such silicon-based semiconductor devices often include metal-oxide-semiconductor (MOS) transistors, such as p-channel MOS (PMOS), n-channel MOS (NMOS) and complimentary MOS (CMOS) transistors, bipolar transistors, BiCMOS transistors and the like.
Each of these semiconductor devices generally includes a semiconductor substrate on which a number of active devices are formed. The particular structure of a given active device can vary between device types. For example, in MOS transistors, an active device generally includes source and drain regions and a gate electrode that controls the current in the channel between the source and drain regions.
For proper operation of the MOS device, current should not flow between the source and drain regions of one MOS-type transistor to that of another transistor. During the manufacturing process, however, movement of dopant atoms, such as boron, can occur in the form of diffusion within the solid silicon of the wafer. The diffusion process occurs at elevated temperatures where there is a concentration gradient between dopant atoms external to the silicon wafer and dopant atoms diffusing into the silicon wafer and is typical in connection with forming p-type and n-type regions of a silicon integrated circuit device. Therefore, one important step in the manufacture of such devices is the formation of isolation areas to electrically separate the MOS devices.
Local oxidation of silicon (LOCOS) and shallow trench isolation (STI) are techniques that have been used in the past to limit diffusion in the silicon and to limit leakage current. STI has the advantage of allowing for higher device density by decreasing the required width of the semiconductor device isolating structure and can enhance surface planarity, thereby considerably improving critical dimension control during the lithographic process. One of the disadvantages to STI is the formation of sharp corners at the interface of the vertically oriented sidewalls and the top surface of the substrate. In efforts to round these sharp corners, the STI process has been further complicated, resulting in increased cost, decreased throughput and reduced yields.
Many processes used in the fabrication of integrated circuits generate stress in the silicon substrate. Given enough stress, the substrate will yield by forming dislocations that can glide into device regions. Shallow trench isolation processes are known to generate high stress in the silicon substrate. In the STI process, the subsequent oxidation (which generates self-interstitials) and implantation (which generates point defects) can contribute to nucleation of dislocations. Several methods have been developed to minimize the dislocations, including changes to the layout of the device, significant changes to the etch process, changes to the ion implantation process and changes to the annealing of the ion implant damage. High temperature corner oxidation cycles prior to the removal of an overlying nitride layer have typically been used to prevent dislocations, but this approach has not been totally satisfactory and is complicated to implement.
Accordingly, a need exists for developing a method for manufacturing semiconductor devices on semiconductor substrates that addresses the above-mentioned concerns and reduces stress-induced dislocations in the silicon substrate while increasing production yields.
SUMMARY OF THE INVENTION
The present invention is exemplified in a number of implementations and applications, some of which are summarized below. One of the advantages of the present invention is the ease of incorporation of the method of eliminating stress induced dislocations in a substrate into current semiconductor fabrication processes. According to one embodiment, a method of forming a semiconductor structure is described that includes forming a first oxide layer over a substrate and forming a first dielectric material layer, typically silicon nitride, over the first oxide layer. An opening is then etched in the oxide and dielectric layers thereby exposing the substrate. A trench is formed with a desired depth in the substrate within the opening provided, followed by deposition of an insulator material in the trench. The first dielectric layer and a portion of the insulator material are then removed, leaving a portion of the insulator material within the trench. The substrate is thereafter subjected to a high temperature post-sacrificial oxide anneal that promotes viscous flow of the oxide and reduces dislocations in the substrate.
The anneal should preferably be performed after the removal of any overlying nitride layer and prior to the implantation of channel implants. In connection with the present invention, it has been discovered that anneals performed while the overlying nitride layer is still in situ gives rise to only a partial relief of silicon stress; much better stress relief can be obtained by performing the anneal after the nitride layer has been removed.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and the detailed description that follow more particularly exemplify these embodiments.
REFERENCES:
patent: 5516721 (1996-05-01), Galli et al.
patent: 5719085 (1998-02-01), Moon et al.
patent: 5811347 (1998-09-01), Gardner et al.
patent: 5882982 (1999-03-01), Zheng et al.
patent: 5915183 (1999-06-01), Gambino et al.
patent: 5933748 (1999-08-01), Chou et al.
patent: 5994756 (1999-11-01), Umezawa et al.
patent: 6037238 (2000-03-01), Chang et al.
“Stress-induced dislocations in silicon integrated circuits”. P.M. Fahey et al., IBM J. Fes.Develop. vol. 36No. 2, Mar. 1992.
“Stress Analysis of Shallow Trench Isolation for 256K-DRAM and beyond”. T. Kuroi et al., IEDM 1998.
“Characterization and Elimination of Trench Dislocations”. J. Damiano et al., VLSI Symposium 1998.
“Modeling of Cumulative Thermo-Mechanical Stress (CTMS) Produced by the Shallow Trench Isolation Process for 1 Gb DRAM and beyond”. Kim et al., IEDM 1998.
“NMOS Drive Current Reduction Caused by Transistor Layout and Trench Isolation Induced Stress.” (G. Scott, J. Lutze, M. Rubin, F. Nouri, and M. Manley, IEDM Technical Digest, 1999, pp. 827-830.).
A New Leakage Component Caused by the Interaction of Residual Stress and the Relative Position of Poly-Si Gate at Isolation Edge. H. Lee et al., IEDM 1995.
Manley Martin
Nouri Faran
Crawford PLLC
Philips Semiconductors Inc.
Smith Matthew
Yevsikov V.
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