Method for eliminating multiple output switching timing skews in

Details Method for eliminating multiple output switching timing skews in Method for eliminating multiple output switching timing skews in

1995-12-20

1998-06-30

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327258, 327295, H03K 515

Patent

active

057740011

ABSTRACT:
A source synchronous computer system to ensure the capturing of signals transmitted from a first component to a second component. An integrated circuit operating on a core clock signal and an I/O clock signal, the circuit comprising a plurality of data drivers and a plurality of delayed I/O clock generators, wherein the I/O clock generators generate delayed I/O clocks signals that follow the I/O clock signal by a phase multiple of the core clock signal. The integrated circuit outputs data through output nodes that are synchronized with I/O clock signal. By outputting data signals in the I/O clock domain and using the delayed I/O clock signals to synchronize transmission with external components, the integrated circuit ensures that the data signals are valid before the external component latches the data. A set of data signals and a delayed I/O clock are generated from similar drivers to further ensure that the data signal is valid before the external component latches the data.

REFERENCES:
patent: 4482826 (1984-11-01), Ems et al.
patent: 4816700 (1989-03-01), Imel
patent: 5015872 (1991-05-01), Rein
patent: 5345109 (1994-09-01), Mehta
patent: 5486783 (1996-01-01), Baumert et al.
patent: 5576652 (1996-11-01), Boehlke

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