Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-06-11
2004-10-26
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C700S110000, C702S059000, C703S014000
Reexamination Certificate
active
06810510
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to circuit area analysis on integrated circuit layouts and in particular, to a method for eliminating false failures saved by redundant paths during circuit area analysis on an integrated circuit layout.
BACKGROUND OF THE INVENTION
Circuit area analysis predicts failures of an integrated circuit that result from probabilistic defects. One common problem with conventional circuit area analysis techniques is their general inability to eliminate false failures saved by redundant paths during the circuit area analysis. This deficiency may result in overly conservative design and unnecessary testing for false failures, both of which add unwarranted cost to the manufacture of the integrated circuit.
OBJECTS AND SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is a method for eliminating false failures saved by redundant paths during circuit area analysis on an integrated circuit layout.
This and additional objects are accomplished by the various aspects of the present invention, wherein briefly stated, one aspect is a method for eliminating false failures saved by redundant paths during critical area analysis of an integrated circuit layout, comprising: identifying vertices significantly encroached by one or more simulated defects; and eliminating false failures resulting from the one or more simulated defects if all nets including at least one of the identified vertices have at least one redundant path that does not include any of the identified vertices.
Another aspect is a method for eliminating false failures saved by redundant paths during critical area analysis of an integrated circuit layout, comprising: identifying vertices significantly encroached by one or more simulated defects; retrieving predefined sets of vertices associated with individual of nets including at least one of the identified vertices; and indicating a failure resulting from the one or more simulated defects for each instance where all elements of at least one of the predefined sets of vertices are one of the identified vertices.
Additional objects, features and advantages of the various aspects of the invention will become apparent from the following description of its preferred embodiments, which description should be taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5452223 (1995-09-01), Zuercher et al.
patent: 5831437 (1998-11-01), Ramadoss et al.
patent: 6247853 (2001-06-01), Papadopoulou et al.
patent: 6317859 (2001-11-01), Papadopoulou
patent: 6334100 (2001-12-01), Ahrikencheikh et al.
patent: 6461882 (2002-10-01), Ishida et al.
patent: 6542830 (2003-04-01), Mizuno et al.
patent: 6618856 (2003-09-01), Coburn et al.
patent: 2002/0053066 (2002-05-01), Richter et al.
Gharaybeh et al., “False-path removal using delay fault simulation”, 1998 Proceeding of Seventh Asian Test Symposium, Dec. 2, 1998, pp. 82-87.*
Fengling et al., “Distinguish real or false fault of single line-to-ground short-circhit for radial distribution network”, 1998 Proceedings of International Conference on Power System Technology, vol. 1, Aug. 18, 1998, pp. 260-264.*
W. Grobman et al., Reticle Enhancement Technology: Implications and Challenges for Physical Design, DAC, 6 pages, Jun. 2001.
D. Woodie, “Chemical Mechanical Polishing Primer”, [Internet], http://www.nnf.cornell.edu/equipment/CMPPrimer.html, 14 pages printed May 18, 2002 (no date).
L-Edit Quick Reference ENGS85, [Internet] http://engineering.dartmouth.edu/~microeng/ledit/ledit.hints.html, 2 pages, Apr. 21, 2001, printed Mar. 22, 2002..
C. G. Levey, “Low Resolution Mask Making Procedure [SIC]”, [Internet] http://thayer.dartmouth.edu/~microeng/ledit/leditlrmask.html, 2 pages, printed Jun. 19, 2003.
Bakarian Sergei
Segal Julie
Garbowski Leigh M.
Heuristics Physics Laboratories, Inc.
Kik Phallaka
Sierra Patent Group Ltd.
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