Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2007-07-03
2007-07-03
Richards, N. Drew (Department: 2809)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S595000, C438S637000, C438S639000, C438S672000, C438S700000
Reexamination Certificate
active
11160688
ABSTRACT:
A via-first dual damascene process is disclosed. When forming trench lines directly above two small pitched, dense via openings having diameter that is substantially equal to the line width of the trench lines, the trench photoresist is biased on the via openings to partially mask the sidewalls of the two dense via openings. By doing this, via-to-via bridging defects can be avoided.
REFERENCES:
patent: 6689695 (2004-02-01), Lui et al.
patent: 6780761 (2004-08-01), Wu et al.
patent: 2003/0199169 (2003-10-01), Jun et al.
patent: 2004/0072430 (2004-04-01), Huang et al.
Chang Kuang-Yeh
Ma Hong
Zhou Wen-Zhan
Hsu Winston
Richards N. Drew
United Microelectronics Corp.
Wagner Jenny L.
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