Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-05-31
2002-04-23
Powell, William A. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S735000, C438S743000
Reexamination Certificate
active
06376389
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to memory devices and more particularly to a method for eliminating the use of anti-reflective coatings in the creation of contacts and formation of local interconnects.
BACKGROUND ART
Memory devices, such as a Flash electrically erasable programmable read only memory (EEPROM), are a class of nonvolatile memory devices that are programmed by hot electron injection and erased by Fowler-Nordheim tunneling or ultra-violet (UV) light.
Each memory cell is formed on a semiconductor substrate (i.e., a silicon die or chip), having a heavily doped drain region and a source region embedded therein. The source region further contains a lightly doped deeply diffused region and a more heavily doped shallow diffused region embedded into the substrate. A channel region separates the drain region and the source region. The memory cell further includes a multi-layer structure, commonly referred to as a “stacked gate” structure or word line. The stacked gate structure typically includes: a thin gate dielectric layer or tunnel oxide layer formed on the surface of substrate overlying the channel region; a polysilicon floating gate overlying the tunnel oxide; an interpoly dielectric layer overlying the floating gate; and a polysilicon control gate overlying the interpoly dielectric layer. Additional layers, such as a silicide layer (disposed on the control gate), a poly cap layer (disposed on the silicide layer), and a silicon oxynitride layer (disposed on the poly cap layer) may be formed over the control gate. A plurality of Flash EEPROM cells may be formed on a single substrate.
After the formation of the memory cells, electrical connections, commonly known as “contacts”, must be made to connect the stack gated structure, the source region and the drain regions to other part of the chip. The contact process starts with the formation of sidewall spacers around the stacked gate structures of each memory cell. An etch-stop layer, typically a nitride material such silicon nitride, is then formed over the entire substrate, including the stacked gate structure, using conventional techniques, such as chemical vapor deposition (CVD). A dielectric layer, generally of oxide, is then deposited over the nitride layer. A layer of photoresist is then placed over the dielectric layer and is photolithographically processed to form the pattern of contact openings. An anisotropic etch is then used to etch out portions of the dielectric layer using the pattern on the photoresist to form source and drain contact openings. The openings at this point reach to the etch stop layer so a second anisotropic etch is used to extend the contact openings to stop at the source and drain regions in the substrate. The photoresist is then stripped, and a conductive material, such as tungsten, is deposited over the dielectric layer and fills the source and drain contact openings to form so-called “self-aligned contacts” (conductive contacts). The substrate is then subjected to a chemical-mechanical polishing (CMP) process which removes the conductive material above the dielectric layer to form the conductive contacts.
In order to connect multiple memory cells together, connections on top of the contacts need to be made. The normal approach is often referred to as Local Interconnect(s) (LI(s)). LIs are used to connect two conductive elements of a semiconductor die. The term “local” refers to the proximity of the two elements with respect to one another. Typically, an etch stop layer is deposed on top of the contacts of devices on a semiconductor and a conductive dielectric or oxide layer is added on top of the etch stop layer. A layer of photoresist is then added and a pattern is formed on its surface using photolithography. Similar to the processes used to create the devices and their contacts, the conductive material is etched away using the pattern formed in the photoresist, and the excess photoresist layer is removed.
As semiconductor devices have shrunk in size, the industry has turned towards deep ultraviolet (DUV) lithography as a photolithographic process to pattern contact openings in sub-0.35 micron line geometry semiconductor devices.
A major obstacle to the miniaturization of semiconductors is the effect of reflectivity in the DWV lithographic and conventional i-line lithographic processes. Reflections occur at the junctions of materials and are influenced in part by the thickness of materials. Because the precision of the photolithographic process is sensitive to such reflections, reducing the reflections by lowering the reflectivity of materials under about 15% is essential. In particular, the differences in thickness caused by the polysilicon, metal, and poly/metal stacks has made small feature patterning and critical dimension (CD) control of photoresist very difficult. Such topography causes unpredictable swings in material reflectivity and needs to be reduced or dampened in some way in order to reduce semiconductor device size. Non-uniformities occurring when the dielectric layer undergoes CMP can increase the total reflectivity from the dielectric to the photoresist during photolithography and cause further disruptions in patterning
To solve this problem, different anti-reflective coatings (ARCs) have been developed which work by phase shift cancellation of specific wavelengths to provide uniform resist patterning. Top anti-reflective coatings (TARCS) are placed on top of the photoresist and are specifically designed so that the reflective light from the resist/ARC interface is equal in amplitude but opposite in phase to the light reflected from the ARC/reflective layer interface.
It has been found that there are certain line width variations which are due to the ARC not being able to reduce the reflective layer reflectivity to a minimum. The reflectivity causes problems with the resist which have been corrected in part by the use of bottom anti-reflective coatings (BARCs) located under the resists. This effectiveness of this additional BARC layer is dependent on the thickness of the oxide layer below it. Although a BARC has the potential to significantly reduce the reflectivity and therefore refine the patterning process, there is a large oxide-thickness dependent swing in the reflectivity.
Another significant problem with ARCs is that they are not transparent to the ultra-violet light normally used when erasing Flash memories. As a result, after the conductive layer in the formation of contacts or local interconnects has occurred, the BARC layer needs to be removed.
Failing to remove the BARC layer would also create capacitance between contacts and interconnects because of its relatively high dielectric constant and would greatly reduce the transistor switching speed. This would add to the adverse speed impact which increases disproportionately with shortened channels. Basically, the parasitic capacitance due to lightly doped drain (LDD) structures as a percentage of the total transistor capacitance is higher for sub-0.18 micron transistors than it is for a 0.18 micron transistor and even worse for a sub-0.13 transistor, making the overall adverse speed impact much more severe in smaller transistors.
Although removal of the ARC is necessary for the above reasons, the actual removal process causes problems. The most significant problem is the cost and complexity in adding ARC removal steps.
Attempts have been made to develop a thin photoresist layer which would allow for the removal of ARC layers as a byproduct of existing etching steps, thus avoiding the additional cost of and complexity. However, it is extremely difficult to deposit and polish a sufficiently thin layer of defect-free photoresist.
Another problem is that the CMP that is used in the removal process of the BARC layer inherently removes portions of the conductive contacts as well as the dielectric layer, producing deep scratches therein. The scratches vary significantly from memory cell to memory cell, creating non-uniformity and adversely affecting device performance.
Rather than use CMP,
Hu Yongzhong
Kinoshita Hiroyuki
Ngo Minh Van
Sahota Kashmir
Subramanian Ramkumar
Ishimara Mikio
Powell William A.
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