Method for eliminating a mask layer during thin film...

Details Method for eliminating a mask layer during thin film... Method for eliminating a mask layer during thin film...

2008-08-26

2010-11-09

Kebede, Brook (Department: 2894)

Semiconductor device manufacturing: process

Making passive device

Resistor

C257SE27047

Reexamination Certificate

active

07829428

ABSTRACT:
A method is disclosed for eliminating a mask layer during the manufacture of thin film resistor circuits. The method of the present invention enables the simultaneous etching of both deep vias and shallow vias using one mask layer instead of two mask layers. A high selectivity film layer of silicon nitride is formed on the ends of a thin film resistor layer. The thickness of the silicon nitride causes the etch time for a shallow via to the thin film resistor to be approximately equal to an etch time for a deep via that is etched through dielectric material to an underlying patterned metal layer.

REFERENCES:
patent: 4843033 (1989-06-01), Plumton et al.
patent: 4847673 (1989-07-01), Matsukawa
patent: 5203957 (1993-04-01), Yoo et al.
patent: 5316978 (1994-05-01), Boyd et al.
patent: 5346585 (1994-09-01), Doan et al.
patent: 5362669 (1994-11-01), Boyd et al.
patent: 5384278 (1995-01-01), Singlevich
patent: 5461000 (1995-10-01), Liang
patent: 5547896 (1996-08-01), Linn et al.
patent: 5814547 (1998-09-01), Chang
patent: 5970374 (1999-10-01), Teo
patent: 6004882 (1999-12-01), Kim et al.
patent: 6097095 (2000-08-01), Chung
patent: 6100154 (2000-08-01), Hsu et al.
patent: 6117789 (2000-09-01), Lee
patent: 6165862 (2000-12-01), Ishikawa et al.
patent: 6171929 (2001-01-01), Yang et al.
patent: 6232194 (2001-05-01), Yaung et al.
patent: 6279585 (2001-08-01), Shiraki et al.
patent: 6297126 (2001-10-01), Lim et al.
patent: 6326256 (2001-12-01), Bailey et al.
patent: 6413835 (2002-07-01), Norstrom et al.
patent: 6417093 (2002-07-01), Xie et al.
patent: 6498385 (2002-12-01), Daubenspeck et al.
patent: 6534374 (2003-03-01), Johnson et al.
patent: 6559047 (2003-05-01), Doohan
patent: 6570239 (2003-05-01), Sakakibara et al.
patent: 6607962 (2003-08-01), Zekeriya et al.
patent: 6645821 (2003-11-01), Bailey et al.
patent: 6680238 (2004-01-01), Song
patent: 6734076 (2004-05-01), Jaiswal et al.
patent: 6737326 (2004-05-01), Steinmann et al.
patent: 6770564 (2004-08-01), Ito et al.
patent: 6809034 (2004-10-01), Ito et al.
patent: 6815305 (2004-11-01), Cha
patent: 6933186 (2005-08-01), Cotte et al.
patent: 7230517 (2007-06-01), Foote, Jr. et al.
patent: 7291525 (2007-11-01), Hill
patent: 7332403 (2008-02-01), Hill et al.
patent: 7410879 (2008-08-01), Hill et al.
patent: 7544579 (2009-06-01), Hill
patent: 7585775 (2009-09-01), Bold et al.
patent: 2002/0132442 (2002-09-01), Kar Roy et al.
patent: 2004/0012071 (2004-01-01), Ido et al.
patent: 2004/0075527 (2004-04-01), Zitzmann et al.
patent: 2004/0129673 (2004-07-01), Belyansky et al.
patent: 2004/0140508 (2004-07-01), Sengoku et al.
patent: 2004/0203241 (2004-10-01), Hampden-Smith et al.
patent: 2005/0003673 (2005-01-01), Mahdavi
patent: 2007/0037386 (2007-02-01), Williams
patent: 2007/0040239 (2007-02-01), Chinthakindi et al.

Affiliated with

Also associated with

Rating

Method for eliminating a mask layer during thin film... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for eliminating a mask layer during thin film..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for eliminating a mask layer during thin film... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4251278