Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1999-01-25
2001-06-05
Metjahic, Safet (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S525000
Reexamination Certificate
active
06242924
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to the art of microelectronic integrated circuits, and more specifically to a method for measuring the surface roughness and size of an internal void in an electrically conductive lead in the metallization pattern of an integrated circuit chip.
2. Description of the Related Art
Microelectronic integrated circuit chips include large numbers of microelectronic devices which are interconnected by one or more layers of metallization. Each layer consists of an intricate pattern of electrically conductive leads made of copper, tungsten, aluminum, etc. Some of the leads can be quite long relative to the overall size of the circuit.
The leads are typically formed by depositing a metal layer on a dielectric layer of the chip, depositing a photoresist layer on the metal layer, photolithographically patterning the photoresist layer to form a mask having openings in which metallization is not desired, and then etching away the exposed metal through the openings in the mask. The photoresist mask is then dissolved away to leave the desired metallization pattern of electrically conductive leads.
The process for forming the metallization layers includes a number of critical variables, and it, as well as subsequent processing steps if not performed with requisite precision, can result in imperfections in the conductive leads. These imperfections are generally of two types, external or surface voids on the surface of a lead, and internal voids within the material of the lead.
As illustrated in
FIG. 1
, an electrically conductive lead
10
has a generally rectangular cross-section, and can have an internal void
12
as a result of imperfect fabrication processing. The lead
10
can also have external or surface voids on its surface. As designated by the reference numeral
14
a
, surface voids can be small, and extend along only a small portion of the width of the lead
10
. The voids can also be larger as indicated at
14
b
, or extend along the entire width of the lead
10
as indicated at
14
c.
Surface voids
14
a
,
14
b
and
14
c
generally have an iso-triangular cross section (the shape of an isosceles triangle) as illustrated at
16
in
FIG. 2
, and can be relatively shallow or deep. The surface roughness of a lead is determined by the number and sizes of surface voids. Internal voids are also known as “seams”, and can also have varied sizes.
Surface roughness of conductive leads due to surface voids has a highly detrimental effect on the electrical performance of an integrated circuit chip, especially with long leads at high frequencies. Surface roughness increases the distance that electrical signals have to travel, thereby creating timing delays and inconsistencies.
Surface roughness also increases the electrical resistance of leads, requiring higher voltages to ensure reliable signal transmission. In extreme cases, many large voids can cause a failure of the circuit to function properly.
Internal voids are also highly detrimental, especially at D.C. or low frequencies. As with external voids, internal voids increase the electrical resistance of the leads and require higher voltages for reliable operation.
Fabrication of integrated circuit chips requires constant monitoring of quality throughout many process steps to ensure that time and expense are not wasted by additionally processing chips that are already defective. A method for monitoring the size and growth of voids in conductive leads as the fabrication processing proceeds is a highly desirable capability for quality control. However, a satisfactory method for achieving this goal has not been heretofore proposed in the art.
SUMMARY OF THE INVENTION
The present invention fills a need which has heretofore existed in the art, and provides a method for monitoring the size and growth of internal and external voids in an electrically conductive lead on a microelectronic integrated circuit chip.
More specifically, the size of an internal void in an electrically conductive lead is measured by determining its electrical resistance at a plurality of A.C. frequencies, ranging from D.C. to a frequency on the order of 50 to 100 GHz at which the majority of current flows along the skin of the lead. The test data is compared with reference data for an electrically conductive reference lead having characteristics which are essentially similar to the test lead.
The difference between the two sets of data increases with the size of an internal void in the test lead. The difference will be greatest at D.C. because the current will flow through substantially the entire cross-section of the lead and the cross-sectional area will be reduced by the internal void. The test data will approach the reference data as the frequency increases because the majority of the current will flow through the skin of the test lead and be less affected by the internal void.
The surface roughness of a lead caused by surface voids is measured by determining its electrical resistance at a frequency high enough that the majority of the current flows through the skin of the lead. The distance at which the surface current flows, and thereby the resistance of the lead, increase with the surface roughness.
These and other features and advantages of the present invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings, in which like reference numerals refer to like parts.
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Joo Young-Chang
Liu Yow Juang W.
Shabde Sunil N.
Yiu Tsui Ting
Advanced Micro Devices
Alexander David G.
Arter & Hadden LLP
Kerveros J
Metjahic Safet
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