Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2003-05-05
2004-09-21
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S687000, C438S358000, C438S390000, C257SE23145
Reexamination Certificate
active
06794288
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of electroless deposition, in particular to a method for electroless formation of phosphorus-containing metal films, such as cobalt-tungsten-phosphorus (hereinafter referred to as Co—W—P) system films on copper substrates with Pd-free activation. Such coatings may find application in semiconductor manufacturing where properties of deposited films and controllability of the composition and of physical and chemical characteristics of the deposited films may be critically important. More particularly, the present invention may find application in processes for fabricating semiconductor devices using a trench wiring technique, such as damascene processes, or the like.
BACKGROUND OF THE INVENTION
Electroless deposition is a process for depositing a thin layer or layers of a material or materials onto a substrate, which normally consists of immersing the substrate in a deposition bath that contains ions of the material to be deposited, whereby some of these ions precipitate onto the surface of the substrate. In contrast to electroplating processes, the electroless deposition process does not need an externally applied electric field to facilitate the deposition process. An advantage of an electroless deposition process is that it can be selective, i.e., the material can be deposited only onto areas that demonstrate appropriate electrochemical properties. Therefore, local deposition can be performed more effectively onto metals that exhibit an affinity to the material being deposited or onto areas pretreated or pre-activated, e.g., with a catalyst. The material or catalyst applied prior to deposition onto the selected areas is sometimes called a “seed material” or “seed layer” and the ratio of the deposition rate on the activated regions to the deposition rate at the non-activated regions is known as the “deposition process selectivity”. It is understood that the deposition rate may also depend on such characteristics of the activated areas, as dimensions, profiles of the exposed surfaces, and distances between the portions of the areas to be activated. For many applications, it is very important to provide deposition of uniform thickness. Other important characteristics of the electroless deposition are selectivity of the process and adherence of the deposited layer to the substrate.
Electroless deposition of various metals from deposition solutions onto catalytically pretreated surfaces has been widely used in the past in the printed circuit board industry for the production of wiring layers and interlayer connections. Later, a similar technique was transfered to semiconductor industry for the production of metal interconnects in semiconductor (IC) chips. The electroless deposition technique is advantageous to other known metal deposition techniques such as different types of sputtering and evaporations. One advantage is the use of less expensive equipment. Another advantage is selectivity and controllability of the process. For example, deposition can be performed only onto pretreated areas. As a result, it becomes possible to reduce the number of lithographic and etching steps, which are the most expensive stages of the semiconductor manufacture. Another advantage is that electroless deposition well matches the present trend for using copper as interconnect materials instead of aluminum, suicides, or the like. It is well known that the new generations of LSI are associated with the use of copper, which possesses very high electrical conductivity. The problem encountered by traditional techniques (that include anisotropic etching) in transfer to copper is that copper is difficult to etch anisotropically. Yet another advantage of electroless deposition is that it to a lesser degree depends on such features of the substrate surface as angles or depth of trenches and vias, etc. This property enables deposition into deep via holes on substrates that could not be uniformly covered by sputtering and evaporation.
Many surface activation techniques that precede electroless deposition are known in the art. The most common applications of electroless deposition to integrated circuit manufacturing comprise deposition of nickel, cobalt, palladium, or copper onto one of two types of substrate surfaces. The first type of substrate surface comprises conductive regions of substrates that are generally formed of silicon, aluminum, or aluminum alloys. The second type of substrate comprises a non-conductor such as silicon dioxide or a polymeric insulator. The reported surface activation techniques applied to these substrates usually fall into one of four categories: (1) catalyst film deposition by evaporation or sputtering, (2) catalyst film deposition by electrochemical or chemical surface modification, and (3) catalytic film deposition from a colloidal suspension; (4) photon-enhanced activation by laser or wide spectrum irradiation.
Metals of Group VIII (e.g., palladium and platinum) are frequently used as catalytic surface activators in electroless deposition methods. Catalytic films of palladium or platinum for subsequent electroless deposition can be readily deposited by evaporation or sputtering techniques. The films deposited with these techniques can be patterned by well-known lithographic techniques, e.g., subtractive etching or liftoff. Large features and/or dense patterns of small features are relatively easy to plate with this method.
It has been found out that in electroless deposition, palladium activation from an aqueous solution demonstrates higher catalytic activity of films than of palladium films deposited by sputtering or evaporation (see U.S. Pat. No. 6,180,523 issued in 2001 to Chwan-Ying Lee, et al.). The reduced catalytic activity results in the formation of a less uniform films. Furthermore, it becomes more difficult to deposit a film on small and isolated features such as metallization patterns on semiconductor devices.
There are known various methods suitable for improving catalytic activity of the surface with the use of palladium prior to electroless deposition.
As has been mentioned above, copper is not easily dry-etched. Therefore, in the formation of a copper wiring, a process of forming a trench wiring is promising. The trench wiring is produced by a process in which a predetermined trench is preliminarily formed in an interlayer dielectric comprised of, for example, silicon oxide, and the trench is plugged with a wiring material. Then, the excess wiring material is removed by, for example, a chemical mechanical polishing (hereinafter, frequently referred to simply as “CMP”) process, to thereby form a wiring in the trench.
The copper wiring is generally used in the form of a multilayer wiring. When such a multilayer copper wiring is formed, no barrier film, which prevents copper from diffusing, is present on the surface of the copper wiring. Therefore, before an upper layer wiring is formed on the copper wiring, as a diffusion-preventing film for copper, a barrier film comprised of silicon nitride, carbon nitride or the like is formed on the copper wiring. Silicon nitride, silicon carbide, and silicon oxynitride have relative dielectric constants larger than that of silicon oxide. Therefore, it is considered that these are advantageous in a method in which the surface of copper after the CMP process is selectively coated with these. In addition, U.S. Pat. No. 5,695,810 issued to V. Dubin, et al. on Dec. 9, 1997 discloses a method in which the surface of copper is coated with a cobalt tungsten phosphorus (Co—W—P) film. In this method, cobalt tungsten phosphorus is deposited by an electroless plating method using the surface of copper as a catalyst.
A disadvantage of the above method is that it offers deposition of a Co—W—P barrier layer onto copper using copper as a catalyst without additional activation. Such a process is characterized by a low deposition rate, which could be improved with the use of catalytic activation.
Further, Japanese Patent Application Laid-Open Specification No. 9-307234 filed
Ivanov Igor C.
Kolics Artur
Petrov Nicolai
Ting Chiu
Blue29 Corporation
Conley & Rose, P.C.
Fourson George
Lettang Mollie F.
Pham Thanh
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