Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-01-31
2002-07-30
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06427224
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the testing of computer system designs by software simulation, and more particularly to a verification methodology which increases the efficiency of verification of system-on-chip (SOC) designs which include an embedded processor.
The complexity and sophistication of present-day integrated circuit (IC) chips have advanced significantly over those of early chip designs. Where formerly a chip might embody relatively simple electronic logic blocks effected by interconnections between logic gates, currently chips can include combinations of complex, modularized IC designs often called “cores” which together constitute an entire “system-on-a-chip”, or SOC.
In general, IC chip development includes a design phase and a verification phase for determining whether a design works as expected. The verification phase has moved increasingly toward a software simulation approach to avoid the costs of first implementing designs in hardware to verify them.
A key factor for developers and marketers of IC chips in being competitive in business is time-to-market of new products; the shorter the time-to-market, the better the prospects for sales. Time-to-market in turn depends to a significant extent on the duration of the verification phase for new products to be released.
As chip designs have become more complex, shortcomings in existing chip verification methodologies which extend time-to-market have become evident.
Typically, in verifying a design, a simulator is used. Here, “simulator” refers to specialized software whose functions include accepting software written in a hardware description language (HDL) such as Verilog or VHDL which models a circuit design, and using the model to simulate the response of the design to stimuli which are applied by a test case to determine whether the design functions as expected. The results are observed and used to de-bug the design.
In order to achieve acceptably bug-free designs, verification software must be developed for applying a number of test cases sufficient to fully exercise the design in simulation. In the case of SOC designs, the functioning of both the individual cores as they are developed, and of the cores interconnected as a system must be verified. Moreover, a complete SOC design usually includes an embedded processor core; simulation which includes a processor core tends to require an inordinate amount of time and computing resources, largely because the processor is usually the most complex piece of circuitry on the chip and interacts with many other cores.
Typically, verification of a SOC which includes an embedded processor core involves using a simulator to simulate software models of the processor and a memory for containing instructions for execution by the processor. Processor-specific instructions are loaded into the memory model, and the simulator simulates execution of the instructions by the processor model, which typically includes interaction by the processor model with other cores in the overall SOC.
Because processor-specific instructions (i.e., instructions in the processor's native assembly language) are low-level, a number of instructions are typically required to perform a function which could otherwise be implemented in a single high-level instruction. Moreover, for accurate simulation, many simulation cycles are required for each processor-specific instruction. As cores are added to a design and verification programs grow in complexity, the simulation time required for verification approaches a prohibitive level. Most commercially available simulators do not provide the processing power to effectively verify an SOC including an embedded processor in a timely manner using the above-described approach. Thus, a verification engineer must either extend the verification phase to unacceptable lengths or end verification prior to fully exercising the design.
It can be appreciated from the foregoing that verification of an SOC can severely impact time-to-market, in particular when the SOC design includes an embedded processor core, as noted above. Accordingly, a verification methodology is needed which addresses the problems described above.
SUMMARY OF THE INVENTION
In a method according to the present invention, verification software for testing a SOC design including an embedded processor core is partitioned into high-level control code and low-level device driver code. The high-level code performs such functions as decision-making, test initialization, test randomization, multi-tasking, and comparison of test results with expected results. The low-level code interfaces with a core being simulated, to apply the test case generated by the upper-level code on a hardware level of operations.
The partitioning of the verification software as described above allows for a “split-domain” mode of verification in which only the low-level code is executed by a simulated processor model, while the rest of the code executes externally to the simulator.
In an embodiment, an interface between the upper-level code executing externally, and the low-level code executing on the simulated processor is provided. The interface handles requests from the high-level code to the low-level code to perform work. A shared area in a model memory, accessible to both upper and lower-level code, is used to control execution of the lower-level code.
Because most of the verification software executes externally to the simulator, for example, on a workstation, while only the low-level code executes on the simulated processor, the overhead of performing the high-level functions noted above is removed from the simulator. Consequently, the number of simulator cycles required to execute a verification test is greatly reduced, while still allowing for realistic testing in which the processor model emits the I/O operations which will ultimately be performed by a physical implementation. As a result, faster verification and reduced time-to-market is enabled.
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Devins Robert J.
Kautzman Mark E.
Mahler Kenneth A.
Milton David W.
Connolly Bove & Lodge & Hutz LLP
International Business Machines - Corporation
Kotulak, Esq. Richard M.
Siek Vuthe
LandOfFree
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