Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Patent
1996-03-05
1999-03-30
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
711209, G06F 1200
Patent
active
058901949
ABSTRACT:
A method for connecting a DRAM module to memory portions of a main processor and memory management PCB board assembly (MPMA PBA) included in a main processor hardware (MPH) block and adapted to perform a higher-order control in a full electronic exchange. In accordance with this method, the DRAM, which is of the zigzag-in-line package type, is replaced by that of the module type so that its parity DRAM area is integrated with memory areas included in the DRAM, thereby enabling waste memory portions of the parity DRAM area to be efficiently managed. A common RAS control signal is divided into a plurality of signals respectively adapted to be used as control signals for defining respective memory areas of the DRAM along with other control signals, namely, CAS and WE control signals. A basic address for the DRAM is determined to obtain an easy memory expansion.
REFERENCES:
patent: 5270964 (1993-12-01), Bechtolsheim et al.
patent: 5357624 (1994-10-01), Lavan
patent: 5383148 (1995-01-01), Testa et al.
patent: 5394538 (1995-02-01), Wada et al.
patent: 5611064 (1997-03-01), Maund et al.
patent: 5613094 (1997-03-01), Khan et al.
Hyundai Electronics Industries Co,. Ltd.
Langjahr David
Swann Tod R.
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