Method for efficient inter-processor communication in an...

Details Method for efficient inter-processor communication in an... Method for efficient inter-processor communication in an...

2008-01-01

2008-01-01

Rinehart, Mark H. (Department: 2111)

Electrical computers and digital data processing systems: input/

Interrupt processing

C711S114000, C710S261000, C710S262000, C710S266000, C710S268000

Reexamination Certificate

active

07315911

ABSTRACT:
A fault-tolerant RAID system is disclosed. The system includes redundant RAID controllers coupled by a PCI-Express link. When a PCI-Express controller of one of the RAID controllers receives a PCI-Express memory write request transaction layer packet (TLP), it interprets a predetermined bit in the header as an interrupt request flag, rather than as its standard function specified by the PCI-Express specification. If the flag is set, the PCI-Express controller interrupts the processor after storing the message in the payload at the specified memory location. In one embodiment, an unused upper address bit in the header is used as the interrupt request flag. Additionally, unused predetermined bits in the TLP header are used as a message tag to indicate one of a plurality of message buffers on the receiving RAID controller into which the message has been written. The PCI-Express controller sets a corresponding bit in a register to indicate which message buffer was written.

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