Method for efficient I/O controller processor interconnect...

Details Method for efficient I/O controller processor interconnect... Method for efficient I/O controller processor interconnect...

2011-07-05

2011-07-05

Lee, Chun-Kuan (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S022000

Reexamination Certificate

active

07975090

ABSTRACT:
A system for I/O controller-processor interconnect coupling supporting a push-pull DMA read operation, in one aspect, may comprise a processor interconnect comprising a plurality of caches and memory subsystems and an I/O controller coupled with the processor interconnect. The I/O controller may comprise a plurality of DMA read request queues, a DMA read slot pool comprising a plurality of DMA read slots, and an expander logic determining a priority of requests in said request queues.

REFERENCES:
patent: 2004/0139305 (2004-07-01), Arimilli et al.
patent: 2006/0259648 (2006-11-01), Agarwala et al.

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