Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-07-25
2006-07-25
Whitmore, Stacy A. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C714S733000
Reexamination Certificate
active
07082591
ABSTRACT:
A chip stack includes a field programmable gate array (FPGA) and an auxiliary component coupled to the FPGA with intercommunicated clock, control and/or data signals. The auxiliary component has a functionality mapped into the FPGA. The pin definition of the FPGA is redefined so that the FPGA and the auxiliary component in combination operate as a modified FPGA. A test circuit is programmed into the FPGA to exercise the auxiliary component to test functionality and timing performance at full speed. The functionality of the auxiliary component mapped into the FPGA is parameterized, such as for the data word width for reading and/or writing data words of different lengths into the auxiliary component in both an aligned and nonaligned manner. A memory interface allows multiple auxiliary circuits to be accessed through the FPGA either together to generate a wider data word or serially to achieve a greater memory depth.
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Ouaiss, I, et al., “Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers”, IEEE, Mar. 2001, pp. 650-657.
Irvine Sensors Corporation
McDermott Will & Emery LLP
Whitmore Stacy A.
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