Method for effective capacitance calculation of interconnect...

Details Method for effective capacitance calculation of interconnect... Method for effective capacitance calculation of interconnect...

2000-10-04

2004-03-02

Whitmore, Stacy (Department: 2812)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C703S004000

Reexamination Certificate

active

06701497

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method for calculating an effective capacitance in an electronic circuit unit coupling a plurality of electronic circuit elements with interconnect portions, particularly in a semiconductor integrated circuit device coupling a plurality of cells with interconnect portions, a method for calculating delay using the same, and a method for constructing a cell library therefor. More particularly to an effective method for calculating delay suitable for designing an electronic circuit unit or an integrated circuit device using a computer and/or verifying the design file therefor.
BACKGROUND OF THE INVENTION
In recent design of increasingly complex semiconductor integrated circuit devices, calculation of delay is very important and a high-speed and high precision delay calculation method is required for designing a high performance semiconductor integrated circuit device. The calculation of delay is also important for the verification of design files, thus a higher calculation accuracy is required for assuring the operation of semiconductor integrated circuit devices to be produced.
In the semiconductor integrated circuit devices which are growing increasingly, the dynamic calculation method of delay such as a circuit simulation may take too much times for processing and may be difficult to use in practice. As methods for calculating delay quickly to the date, some static delay calculation methods have been used by calculating cell delay based on the cell load capacitance and input transition to calculate interconnect delay from the interconnect resistance and interconnect capacitance.
However, the processing technology of the semiconductor integrated circuits tends to become more finer than ever so that the increase of cell driving power together with the increase of interconnect resistance may enhance the shielding effect that may result in the apparently smaller load capacitance in the output of cell than the actually total load capacitance. Some simple delay calculation method may result in unacceptable errors.
A high-precision delay calculation method that can take into account the shielding effect is the calculation method using the effective length of interconnection, disclosed in the Japanese Unexamined Patent Publication No. H9-298242. By using the interconnect effective length, the load delay calculation of semiconductor integrated circuits using interconnections having some resistance may be allowed to perform at higher precision and higher speed.
In the delay calculation method using the interconnect effective length in the prior art, there is a problem that since the interconnect effective length may differ according to the combination of cell driving power and the interconnection type, a huge quantity of data must be gathered prior to delay calculation, as well as many process steps are required at the time when changing cells or changing devices, and changing the interconnection parameter, so that the designing period of semiconductor integrated circuit device is prolonged because of such a number of process steps.
In particular, for the design of a high performance semiconductor integrated circuit device, cell design is performed in parallel along with the logic design to attempt to increase the performance, however in such process the increase of the number of process steps for obtaining data may become a serious problem.
More specifically, for a very high speed LSI, which may require high-speed operation of 500 MHz or over, the influence brought by the parasitic interconnect resistance may be considered to be considerably, a designing and producing methodology of integrated circuit devices using a calculation method of signal delay of higher precision and higher efficiency is needed.
An object of the invention is to provide an improved method for effective capacitance calculation of interconnection portion and delay calculation of electronic circuits.
SUMMARY OF THE INVENTION
The present invention has been made in view of the above circumstances and has an object to overcome the above problems and to provide, by substituting the impedance of interconnection portion placed between a first node of the output section of first electronic circuit element and a second node of the input section of second electronic circuit element with an equivalent circuit of RC &pgr; type having an equivalent capacitance C
1
placed on the side of the second node, an equivalent capacitance C
2
placed on the side of the first node and an equivalent resistance R placed between these both equivalent capacitors, and defining delay from the first electronic circuit element to the first node as t
0
, a method of calculation at higher precision of effective load capacitance Ceff viewed from the first node as C
2
+C
1
·t
0
/(t
0
+R·C
1
), as well as a method of calculation of the delay T of the electronic circuit, based on thus calculated effective load capacitance Ceff, by using the input transition time TI of the electronic circuit element previously determined by simulation and delay parameters a, b, c, and d, according to an equation T=a·TI·Ceff+b·Ceff+c·TI+d.
In accordance with an aspect of the present invention, a method of calculation of signal delay in a semiconductor integrated circuit device, the method of calculation of cell delay having the processes of:
(a-1) calculating temporary load delay T
1
that is the load delay of the cell from the capacitance Ct that is the sum of all of values of capacitances connected to the output of the cell;
(a-2) calculating temporary RC delay T
2
that is the delay in the load itself from the resistance and capacitance of the load connected to the output of the cell;
(a-3) calculating effective load capacitance Ceff from the temporary load delay T
1
and the temporary RC delay T
2
;
(a-4) calculating cell delay Tc based on the effective load capacitance Ceff.
In accordance with another aspect of the present invention, a method of calculating signal delay in a semiconductor integrated circuit device, the calculation method of delay in interconnection connected to a cell having the processes of:
(b-1) calculating output transition time TT
1
of the cell from the capacitance Ct that is the sum of all of value of capacitances connected to the output of the cell;
(b-2) calculating output transition time TT
2
of the cell from the effective load capacitance Ceff;
(b-3) calculating temporary interconnection delay Tw
0
from the input capacitance Cci of the load cell Celli connected to the interconnection resistance Rw and the interconnection capacitance Cw in the interconnections connected to the cell and;
(b-4) calculating interconnection delay Tw from the output transition time TT
1
and the output transition time TT
2
and the temporary interconnection delay Tw
0
.
Additional objects and advantages of the invention will be set forth in part in the description which follows and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentality and combination particularly pointed out in the appended claims.


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patent: 6496960 (2002-12-01), Kashyap et al.
patent: 6510404 (2003-01-01), Kuriyama et al.

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