Method for edge profile and design rules control

Details Method for edge profile and design rules control Method for edge profile and design rules control

1997-06-18

1999-03-02

Powell, William

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

438734, 438743, 438756, 438666, H01L 2100

Patent

active

058770925

ABSTRACT:
A method is described which uses the differential etch behaviour of two different kinds of sequentially deposited silicon oxide layers in conjunction with controlled thicknesses and etching conditions to allow the etching of features such as via contact holes, oxide sidewalls, and crossover insulation edges to produce non-abrupt step height profiles for better edge coverage while still maintaining close adherence to minimum spacing design ground rules between adjacent features.

REFERENCES:
patent: 4372034 (1983-02-01), Bohr
patent: 4888087 (1989-12-01), Moslehu et al.
patent: 4902377 (1990-02-01), Berglund et al.
patent: 5180689 (1993-01-01), Liu et al.
patent: 5470790 (1995-11-01), Myers et al.
patent: 5629237 (1997-05-01), Wang et al.
patent: 5672241 (1997-09-01), Tien et al.

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