Method for early logic mapping during FPGA synthesis

Details Method for early logic mapping during FPGA synthesis Method for early logic mapping during FPGA synthesis

2006-04-26

2009-06-02

Garbowski, Leigh Marie (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07543265

ABSTRACT:
Programming software defining an algorithm that provides improved power, area and frequency predictability of a logic design early in the synthesis flow process, prior to Technology Mapping, without degrading the power, speed or area of the design implementation for PLDs. The method of the algorithm involves performing a high level synthesis of the logic to generate a netlist, performing a multilevel synthesis on the netlist to generate a gate implementation of the netlist; and performing technology mapping on the gate implementation to map the gate implementation to actual resources on the target device. During the high level synthesis of the logic into the netlist, technology mapping is performed on a selected portion of the logic to improve the predictability of the power, area and/or frequency of the logic design without substantially degrading the performance of the power, area and frequency of the logic design.

REFERENCES:
patent: 5526276 (1996-06-01), Cox et al.
patent: 6195788 (2001-02-01), Leaver et al.
patent: 7171633 (2007-01-01), Hwang et al.
patent: 7337100 (2008-02-01), Hutton et al.
patent: 7360197 (2008-04-01), Schleicher et al.
patent: 7373631 (2008-05-01), Yuan et al.
Altera Corporation, Quartus II Software, Section III, Synthesis Manual, May 2006, Chapters 7-12.

Affiliated with

Also associated with

Rating

Method for early logic mapping during FPGA synthesis does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for early logic mapping during FPGA synthesis, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for early logic mapping during FPGA synthesis will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4070990