Electrical computers and digital processing systems: processing – Architecture based instruction processing – Data flow based system
Reexamination Certificate
1998-09-30
2002-08-27
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Architecture based instruction processing
Data flow based system
C712S213000, C712S211000, C712S248000, C712S217000, C710S041000, C710S104000, C710S120000
Reexamination Certificate
active
06442672
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to data processing structures and methods therefore and, more particularly, to a data processing architecture wherein alternative control mechanisms (i.e. an instruction-decoder and a specialized state machine) may be dynamically bound to a shared functional unit or group of functional units.
2. Description of Related Art
Microprocessors form a critical component of modern electronic devices. Various microprocessor architectures have developed, depending on the intended use of the device. All microprocessors, however, are based around one or more “functional units” or data path circuits that perform a specified operation such as an add function, a subtract function, a shift by one, and so on. The universe of functional units can generally be divided into two varieties: (1) general purpose functional units that may be programmatically controlled by way of an instruction stream and a suitable instruction-decoder and (2) special purpose functional units that are typically optimized to perform a single function (e.g. a multiply) and are typically controlled by a specialized finite state machine (FSM).
Viewing microprocessors as comprising functional units, one can logically see a range of available architectures that extends from a completely general architecture to a completely dedicated architecture. The Pentium processor made by Intel is an example of a completely general architecture, which does not contain any special purpose, dedicated functional units, but rather a plurality of general purpose functional units that are all controlled by an instruction pipeline. The advantage of such a general purpose processor is that all of the functional units are always available for use. Such generality, however, comes at the cost of size and performance because there is an inherently inefficient use of the microprocessors resources.
At the other end of the spectrum are fixed functionality microprocessors that contain only dedicated, special purpose functional units that are controlled by finite state machines. An integrated circuit designed to implement the MPEG-2 video compression standard, for example, is likely to contain such dedicated functional units and strict FSM control because it implements a very limited function.
In between the two extremes or paradigms, various industry members have designed and implemented microprocessors that incorporate both general purpose functional units controlled by an instruction stream, and special purpose functional units controlled by a finite state machine. In all known cases, however, such mixed-functionality microprocessors have implemented a static division or compromise between the two control mechanisms, i.e. between an instruction stream and corresponding instruction-decoder on one hand, and one or more finite state machines on the other hand. The functional units available for control by the various control mechanisms, in other words, are dedicated to those control mechanisms. In the known prior art therefore, the industry has either selected one of the extreme paradigms or has made compromise that was, in some cases, a fixed compromise. A functional unit takes data out of memory, operates on that data, and then puts the result back in memory. A control unit tells the functional unit what data to use or provides the functional unit with that data, depending on the point of view.
Microprocessors on the specialized end of the spectrum are often referred to as digital signal processors or DSPs. DSPs are often used in special purpose electronic devices such as, for example, wireless communication devices (cellular and portable phones) and modems. The DSPs in such devices often implement mathematically intensive algorithms such as Viterbi decoding, REED-SOLOMON decoding, and Fast Fourier Transforms, to name a few.
The processor architectures which have made a fixed compromise between general purpose and specialized functional units and appropriate control therefore have generally achieved their intended purpose of merging general purpose functionality with specialized, high speed data processing functionality. Such devices, however, are inefficient in that the various functional units, which must be provided to achieve the static compromise, are often idle when the processor executes multiple applications. The result of the static compromise, therefore, is a larger than necessary die-size, a more costly processor, additional power consumption, reduced speed and depending on other limiting issues, restricted applicability to new applications.
There remains a need, therefore, for a processor architecture which will efficiently combine the structures and resulting benefits of general purpose functional units and specialized functional units in such a way that they may be dynamically shared between two or more control mechanisms.
SUMMARY OF THE INVENTION
In one aspect, the invention may be regarded as a method of dynamically sharing a processing unit between multiple control mechanisms, the method comprising the steps of: providing a processing unit; providing an instruction decoder for executing a first program stored in a memory; providing a finite state machine for executing a second program according to the finite state machine; and dynamically assigning the processing unit to the instruction decoder and the finite state machine in accordance with the first and second programs.
In another aspect, the invention may be regarded as a multiprocessor IC comprising: a processing unit; a control pipeline including an instruction decoder and an output for issuing control signals to the processing unit; a finite state machine including an output for issuing control signals to the processing unit; and means for dynamically assigning the control signals from the instruction decoder and the control signals from the finite state machine to the processing unit.
REFERENCES:
patent: 4484268 (1984-11-01), Thoma et al.
patent: 4969148 (1990-11-01), Nadeau-Dosite et al.
patent: 5465377 (1995-11-01), Blaner et al.
patent: 5487024 (1996-01-01), Girardeau, Jr.
patent: 5598546 (1997-01-01), Blomgren
patent: 5713012 (1998-01-01), Tanaka et al.
patent: 5790824 (1998-08-01), Asghar et al.
patent: 5864689 (1999-01-01), Tran
patent: 5903310 (1999-05-01), Finotello et al.
patent: 5940311 (1999-08-01), Dao et al.
patent: 5970241 (1999-10-01), Deao et al.
patent: 6029240 (2000-02-01), Blaner et al.
patent: 6044453 (2000-03-01), Paver
patent: 6049882 (2000-04-01), Paver
“Selecting Predecoded Instructions with a Surrogate”,IBM Technical Disclosure Bulletin, vol. 36, No. 6A, Jun. 1993, pp. 35-38.
C.W. Moser, Jr., “Increasing an Instruction Set Without Increasing Word Length”,Electronics, vol. 48, No. 3, Feb. 1975, pp. 114-115.
Akin Gump Strauss Hauer & Feld & LLP
Conexant Systems Inc.
Pan Daniel H.
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