Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
1999-10-14
2002-08-06
Picardat, Kevin M. (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S734000, C257S735000, C257S787000, C438S106000
Reexamination Certificate
active
06429517
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device and a fabrication method thereof. More particularly, this invention relates to a semiconductor device of the type in which an extension for connecting an electrode terminal of each semiconductor chip and an external connection terminal is sealed by sealing resin, and to a fabrication method of such a semiconductor device.
2. Description of the Related Art
Semiconductor devices, the semiconductor chip of which is mounted on a substrate having substantially the same size as that of the semiconductor chip (hereinafter called the “chip size package”), include the one that is shown in FIG.
10
. In the chip size package shown in
FIG. 10
, the semiconductor chip
100
is mounted on a substrate
102
that is a multi-layered substrate. An electrode terminal
104
of this semiconductor chip
100
and an external connection terminal
106
fitted to the substrate
102
are connected by internal wiring or through a via-hole.
Incidentally, a sealing resin
108
is poured into the space between the semiconductor chip
100
and the substrate
102
, and seals the electrode terminal
104
of the semiconductor chip
100
, and so forth.
The chip size package shown in
FIG. 10
can be employed even when the number of electrode terminals
102
of the semiconductor chip
100
is large.
Because the substrate
102
has the multi-layered structure, however, connection defects of internal wiring or via-holes are more likely to occur inside the substrate
102
. Also, interface exfoliation is likely to occur between the substrate
102
and the sealing resin
108
or between the semiconductor chip
100
and the sealing resin
108
due to the difference of the thermal expansion coefficient between the semiconductor chip
100
and the substrate
102
.
Some of the chip size packages have a construction in which extension leads are extended on one surface of the substrate having the semiconductor chip mounted thereon, and the external connection terminals are bonded to the other surface of the substrate. In the chip size packages of such a type, too, the sealing resin is poured into the space between the semiconductor chip and the substrate and seals the electrode terminals of the semiconductor chip, and so forth. For this reason, interface exfoliation is likely to occur, in such chip size packages, between the substrate and the sealing resin or between the semiconductor chip and the sealing resin. Furthermore, because the extensions formed on one surface of the substrate and the external connection terminals formed on the other surface of the substrate are connected through via-holes, etc, penetrating through the substrate, connection defects between the extensions and the via-holes are likely to occur, too.
In these chip size packages of the prior art, the semiconductor chip is mounted on the substrate that is formed in advance, and needs the substrate formation step. Therefore, the production cost of the chip size packages becomes high.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a semiconductor device that has improved reliability by preventing connection defects with extensions and interface exfoliation between a substrate and a sealing resin, and has reduced production cost due to a simple fabrication process, and also a fabrication method thereof.
The inventors of the present invention have realized that, in order to accomplish the objects described above, it is effective to omit the substrate
102
of the chip size package shown in
FIG. 10
, and have completed the present invention.
In other words, according to one aspect of the present invention, there is provided a semiconductor device of the type in which a lead for electrically connecting an electrode terminal of each semiconductor chip to an external connection terminal comprises an extension extending parallel to an electrode terminal formation surface of the semiconductor chip at a predetermined distance from the semiconductor chip, an external connection terminal post provided at one of the end portions of the extension, and an electrode terminal post provided to the other end portion of the extension and connected to the electrode terminal of the semiconductor chip; wherein the electrode terminal post and the extension are sealed by a sealing resin, and the distal end portion of the external connection terminal post is exposed from the sealing resin.
According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device of the type in which an extension for connecting an electrode terminal to an external connection terminal of each semiconductor chip is sealed by a sealing resin, the method comprising the steps of: serially forming grooves at predetermined positions of a metal plate on which the external connection terminals are to be formed, external connection terminal posts by filling a metal into the grooves, extensions on the metal plate each having one of the ends thereof connected to the external connection terminal post, and electrode terminal posts each having one of the ends thereof connected to the other end portion of the extension and the other end thereof connected to the electrode terminal of the semiconductor chip; mounting the semiconductor chips in such a fashion that the electrode terminals of the semiconductor chips are connected to the other end of the electrode terminal posts; applying first etching to the metal plate from an open surface side on which the grooves are open, to a predetermined thickness in such a fashion as to obtain an etched surface of a metal plate having the predetermined thickness, filling a sealing resin between the etched surface of the metal plate and an electrode terminal formation surface of the semiconductor chips, and resin-sealing the extensions extending from the electrode terminal formation surface of the semiconductor chips with a predetermined distance therefrom, and the electrode terminal posts; and applying second etching to the exposed surface side of the metal plate in such a fashion as to form the external connection terminals at the distal end portion of the external connection terminal posts so exposed, and removing the metal plate.
In the present invention described above, the lead comprising the electrode terminal post, the extension and the external connection terminal post is preferably formed of gold, and this lead made of gold can be easily shaped by electrolytic gold plating using the metal plate as a power feed layer.
The sealing resin for sealing such a lead preferably has a Young's modulus of not greater than 1 GPa at room temperature.
The fitting strength of the external connection terminal can be improved by forming an external connection terminal made of a metal such as a solder at the distal end portion of the external connection terminal post. Such an external connection terminal can be formed by forming a metal layer of a solder, or the like, at the distal end portion of the external connection post by electrolytic metal plating using the metal plate as a power feed layer, and re-flowing the metal layer.
In the semiconductor device according to the present invention, the electrode terminal of the semiconductor chip and the external connection terminal are connected by the lead. Therefore, in comparison with semiconductor devices of the type in which a substrate is interposed between the semiconductor chip and the external connection terminal, the number of connection portions becomes smaller, and the connection defects of the internal wiring and the via-holes can be reduced.
Moreover, because the substrate for mounting the semiconductor chip can be omitted, the problem of the interface exfoliation between the substrate and the sealing resin or between the semiconductor chip and the sealing resin, that results from the difference of the thermal expansion coefficient between the substrate and the semiconductor device, can be eliminated, and the substrate formation step
Horiuchi Michio
Kirloskar Mohan
Takeuchi Yukiharu
Collins D. M.
Picardat Kevin M.
Shinko Electric Industries Co., LTD
Staas & Halsey , LLP
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