Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2008-03-04
2008-03-04
Weiss, Howard (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S624000, C257SE21579, C257SE23167
Reexamination Certificate
active
11341338
ABSTRACT:
A dual damascene interconnect structure having a patterned multilayer of spun-on dielectrics on a substrate is provided. The structure includes: a patterned multilayer of spun-on dielectrics on a substrate, including: a cap layer; a first non-porous via level low-k dielectric layer having thereon metal via conductors with a bottom portion and sidewalls; an etch stop layer; a first porous low-k line level dielectric layer having thereon metal line conductors with a bottom portion and sidewalls; a polish stop layer over the first porous low-k dielectric; a second thin non-porous low-k dielectric layer for coating and planarizing the line and via sidewalls; and a liner material between the metal via and line conductors and the dielectric layers. Also provided is a method of forming the dual damascene interconnect structure.
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Kumar Kaushik A
Malone Kelly
Tyberg Christy S
Morris, Esq. Daniel P.
Ohlandt Greeley Ruggiero & Perle L.L.P.
Weiss Howard
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