Method for dry etching vias in integrated circuit layers

Details Method for dry etching vias in integrated circuit layers Method for dry etching vias in integrated circuit layers

1989-07-10

1991-05-21

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437228, 437233, 437234, 148DIG51, 427 38, 427 39, 156643, 156646, H01L 2100, H01L 2102, H01L 2130, B44C 122

Patent

active

050175114

ABSTRACT:
A process is disclosed through which vias (50) can be formed by the reaction of an etchant species (52) with a mercury cadmium telluride (HgCdTe) or zinc sulfide (ZnS) layer (42). The activating gases (20) are preferably a hydrogen gas or a methane gas which is excited in a diode plasma reactor (100) which has an RF power source (13) applied to one of two parallel electrodes. The etching occurs in selected areas in a photoresist pattern (44) residing over the ZnS or HgCdTe layer (42). Wet etching the layer (42) with a wet etchant (54) following the dry etching, improves the via (50) by making the walls (48) smoother, and allowing for expansion of the vias (50) to a dimension necessary for proper operation of a HgCdTe-based infrared detector.

REFERENCES:
patent: 4436761 (1984-03-01), Hayashi et al.
patent: 4579609 (1986-04-01), Reif et al.
patent: 4698128 (1987-10-01), Berglund et al.
patent: 4818326 (1989-04-01), Liu et al.
Ghandhi, S., VLSI Fabrication Principles, Wiley & Sons, Chap. 9, p. 523, 1983.
Spencer, J., Stoichiometric Dry Etching of Mercury Cadmium Telluride Using a Secondary Afterglow Reactor, J. Vac. Sci. Technol. A, Vac. Surf. Films (USA), vol. 7, No. 3, pt. 1, pp. 676-681, Jun. 1989.

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