Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-12-18
2003-09-02
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C382S274000, C375S308000
Reexamination Certificate
active
06615398
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for dividing a read only memory (ROM) of a digital frequency synthesizer that synthesizes a frequency in a communication system, which can reduce a size of the ROM.
DESCRIPTION OF THE PRIOR ART
A direct digital frequency synthesizer (DDFS) is used to synthesize frequencies in a communication system requiring fast frequency conversion.
FIG. 1
is a block diagram illustrating a simplified direct digital frequency synthesizer (DDFS).
The DDFS includes a phase accumulator
11
for adding input phase and outputting a p-bit phase value, a first complementer
12
for outputting a p-2-bit phase value except the most significant bit (MSB) and the second most significant bit (and the second MSB) out of the p-2-bit phase values directly or with the help of a complement in accordance with the second most significant bit (2
nd
MSB) among the p-bit phase values, a lookup table
13
for storing m-1-bit sine value according to the phase value, and a second complementer
14
for outputting the m-1-bit sine value directly or with the help of a complement according to the MSB value among the p-bit phase values, and a digital/analog converter
15
for outputting a sine value from the second complementer
14
into an analog sine value.
A frequency value that the DDFS wants being inputted in an N-bit digital value, the DDFS outputs a sine waveform corresponding to the frequency value.
To describe the operation of the DDFS in detail, the phase accumulator
11
receives an N-bit frequency input word (&Dgr;&PHgr;) of, accumulates it and outputs a p-bit phase value. The p-bit phase value has a range of 0~2&pgr; rad. Among the p-bit phase values, the 1 bit of the most significant bit (MSB) determines the sign of the result, and the second MSB determines whether the sine waveform should increase or decrease. Among the output bits of the phase accumulator
11
, the remaining p-2 bits except the two most significant bits are used as addresses of the ROM lookup table
13
. Therefore, the p-2 bits of the phase values are in the range of 0~&pgr;/2 rad.
The p-2 bits of phase values are inputted to a first complementer
12
, which outputs p-2-bit phase values directly if the second MSB of the p-bit phase value is 0, and if it's 1, the first complementer
12
outputs p-2-bit phase values by taking a complement of p-2-bit phase values. The values outputted from the first complementer are inputted into a ROM lookup table
13
, which uses the output values of the first complementer
12
as address and outputs m-1-bit sine values. The m-1-bit sine values are inputted into the second complementer
14
. The second complementer
14
outputs the m-1-bit sine values directly or by taking a complement according to the MSB value of the phase accumulator
11
among its output values. In short, if the MSB is 0, the m-1-bit sine values are outputted directly, and if it's 1, the m-1-bit sine values are outputted by taking a complement. The digital/analog converter
15
converts the output values of the second complementer
14
into analog sine waves.
The ROM lookup table
13
does not store all the sine values in the range of 0~2&pgr; but all the sine vales in the range of 0~&pgr;/2 in m-1 bit by using the symmetry of a sine waveform. That is, the size of the ROM lookup table
13
is (m-1)×2
p-2
.
In the DDFS, the ROM lookup table
13
consumes electric power most, and many methods for reducing the size of a ROM lookup table, a ROM in short, have been suggested to run the ROM lookup table in low power. Among the method is a modified Nicholas architecture, which divides a ROM into two and thus reduces power consumption and the size.
When p-2-bit phase values are divided into a significant bit (&agr;), an intermediate bit (&bgr;) and an insignificant bit (&ggr;), the sine value
sin
(
π
2
(
α
+
β
+
γ
)
)
corresponding to a certain phase value (&agr;+&bgr;+&ggr;) is as shown in a following equation 1.
sin
(
π
2
(
α
+
β
+
γ
)
)
=
sin
(
π
2
(
α
+
β
)
)
cos
(
π
2
γ
)
+
cos
(
π
2
(
α
+
β
)
)
sin
(
π
2
γ
)
≈
sin
(
π
2
(
α
+
β
)
)
+
cos
(
π
2
α
)
sin
(
π
2
γ
)
Eq
.
1
Here, the ROM is divided into a coarse ROM and a fine ROM, the value of
sin
(
π
2
(
α
+
β
)
)
is stored in the coarse ROM, and the value
cos
(
π
2
α
)
sin
(
π
2
γ
)
stored in the fine ROM. Thus, the size of the ROM can be reduced, and instead of
sin
(
π
2
(
α
+
β
)
)
,
[
sin
(
π
2
(
α
+
β
)
)
-
(
α
+
β
)
]
is stored in the coarse ROM and &agr;+&bgr; is added to it later on. Consequently,
[
sin
(
π
2
(
α
+
β
)
)
-
(
α
+
β
)
]
is stored in the coarse ROM and
cos
(
π
2
α
)
sin
(
π
2
γ
)
,
in the fine ROM.
When a phase value (&agr;+&bgr;+&ggr;) is inputted from the first complementer, a digital sine value is obtained by calculating the data of the coarse ROM and the data of the fine ROM in the following equation 2.
sin
(
π
2
(
α
+
β
+
γ
)
)
≈
[
sin
(
π
2
(
α
+
β
)
)
-
(
α
+
β
)
]
+
(
α
+
β
)
+
cos
(
π
2
α
)
sin
(
π
2
γ
)
Eq
.
(
2
)
Suggesting a method of reducing the ROM size by dividing the entire ROM into a coarse ROM and a fine ROM, the modified Nicholas architecture described above can reduce electric power consumption to what extend. However, being an element with a great deal of power consumption, the size of the ROM still has much more room to be reduced and no method has been suggested for it.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a ROM division method for reducing power consumption and the ROM size by minimizing the size of the ROM, which is an element with most power consumption in a digital frequency synthesizer, and a digital frequency synthesizer adopting the same method.
In accordance with an aspect of the present invention, there is provided a method for dividing a read only memory (ROM), comprising the steps of: a) when an original ROM has k bits of input data (k being a natural number bigger than 1), 2
k
numbers of input addresses, c bits of output (c being a natural number bigger than 1) and original data stored on the original ROM are divided into 2
i
(1≦i≦k) numbers of sections, storing the smallest value of each section in a q-bit (1≦q≦c) quantized ROM; and b) storing in an e-bit error ROM, an the error value between the original data of the original ROM and the quantized value of the quantized ROM at all (2
k
numbers of) input addresses of the original ROM (e being the smallest number of bits for expressing all errors at all input address of the original ROM).
In accordance with another aspect of the present invention, there is provided a digital frequency synthesizer with a ROM lookup table that divides and stores the sine value corresponding to an input phase value into a coarse ROM and a fine ROM, adds the two ROM values and outputs the sine value corresponding to the phase value, the coarse ROM comprising: a coarse-quantized ROM for storing the smallest value of each section in q1 bits (1≦q1≦c1), when the coarse ROM has 2
k1
(k1 being a natural number bigger than 1) numbers of input addresses and c1 numbers of output addresses (c1 being a natural number bigger than 1) and the data in the coarse ROM are divided into 2
i1
(1≦i1≦k1) numbers of sections; and a coarse-error ROM for storing the all error values between the data value of the coarse ROM and the quantized value of the coarse-quantized ROM at all input addresses (2
k1
) of the coarse ROM in e1 bits (e1 being th
Han Seon-Ho
Kim Lee-Sup
Kim Seong-Do
Kim Young-Jun
Park Mun Yang
Electronics and Telecommunications Research Institute
Garbowski Leigh M.
Jacobson & Holman PLLC
Liu Andrea
LandOfFree
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