Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-04-13
2003-02-18
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06523160
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for dividing a terminal in automatic interconnect routing processing for a semiconductor device, to a computer program for implementing that method, and to an automatic interconnect routing processor using this method. More particularly, it relates to a method for dividing functional block terminals suitable for the case in which a functional block terminal used in automatic interconnect routing straddles across a plurality of interconnect intersections of wiring grids.
2. Related Art
In conventional automatic interconnect routing processing as shown in
FIG. 17
, in the case in which a functional block terminal
100
straddles across a plurality of interconnect intersections of wiring grids (the five locations A, B, C, D, and E are shown in
FIG. 17
) in performing automatic interconnect routing processing, there is the problem that the functional block terminal
100
are used as part of the automatic interconnects.
For example, in the case in which a plurality of inverters INV
1
to INVn are connected in parallel, when a wiring of an INV
2
is made via terminal E, because it is not possible to determine the capacitance and resistance of the input terminal of the INV
2
, it is not possible to accurately perform the timing verification. For this reason, although no problem will occur in the timing verification, there is a timing problem occurring in the actual product.
For solving this problem in the prior art, a functional block terminal is defined as terminal rectangle area that includes one wiring grid. In this case, when one terminal is used, there was the problem of not being able to use the above-mentioned terminals again.
As shown in
FIG. 18
, in the case in which there is a terminal F on a wiring grid and an interconnect G is connected to the terminal F, an interconnect prohibition area is defined by providing the interconnect G, so that an interconnect H is connected to the terminal F, while making contact with the interconnect G.
In this case, because an interconnect prohibition area is defined and there is contact between interconnect H and the interconnect G, so that an error occurring in performing automatic interconnect routing is detected. Therefore, the interconnect H is not connected to the terminal F by the automatic interconnect routing processing.
Accordingly, it is an object of the present invention to eliminate setting errors and the like in an automatic interconnect routing processing, so as to perform automatic interconnect routing processing with high good efficiency.
SUMMARY OF THE INVENTION
To achieve the above-noted objects, the present invention adopts the following base technical constitution.
Specifically, a first aspect of the present invention is a method for dividing a terminal into a plurality of terminal units in automatic interconnect routing processing in a semiconductor device, the method comprising the steps of: reading in functional block layout information of the semiconductor device from an external memory device, separating the functional block layout information into input/output terminal information, non-input/output terminal information, and wiring grid information for wiring grids, and storing the input/output terminal information, the non-input/output terminal information, and the wiring grid information in an internal memory device, recalling wiring grid information stored in the internal memory device, setting auxiliary wiring grids at an intermediate point between the wiring grids adjacently arranged to each other in the X direction and at an intermediate point between the wiring grids adjacently arranged to each other in Y direction, and storing the auxiliary wiring grid information including the auxiliary wiring grids in the internal memory device, recalling the input/output terminal information and the auxiliary wiring grids information stored in the internal memory device, and overlapping the terminal and the auxiliary wiring grids, dividing a wiring area of the semiconductor device into a first region and a second region wherein the first region is an area formed by being surrounded with the auxiliary wiring grids adjacently arranged to each other in X-direction and being adjacently arranged to each other in Y-direction and including the terminal provided on a crossing point at which the auxiliary wiring grid in X-direction and in Y-direction are intercrossed to each other and the second region which does no include the terminal over the crossing point so as to define a top side, a bottom side, a left side and a right side of the first region, moving the top, bottom, left, and right sides of the first region outward so as to expand the first region, respectively, until each side comes into contact with or overlaps an adjacent first region, and dividing the terminal into a plurality of first regions expanded by moving the sides, and storing the dividing information as the terminal units in the external memory device.
A second aspect of the present invention is a method for dividing a terminal into a plurality of terminal units in automatic interconnect routing processing in a semiconductor device, the method comprising the steps of: reading in functional block layout information of the semiconductor device from an external memory device, separating the functional block layout information into input/output terminal information, non-input/output terminal information, and wiring grid information for wiring grids, and storing the input/output terminal information, the non-input/output terminal information, and the wiring grid information in an internal memory device, recalling the input/output terminal information and the wiring grids information stored in the internal memory device, and overlapping the terminal and the wiring grids, extracting a terminal portion, which is a part of the terminal, overlapped an intersection of the wiring grids in X-direction and Y-direction, forming a terminal region which includes the terminal portion, and forming a top side, a bottom side, a left side and a right side so as to surround the terminal region, moving the top, bottom, left, and right sides of the terminal region outward so as to expand the terminal region, respectively, until each side comes into contact with or overlaps an adjacent terminal region, and dividing the terminal into a plurality of terminal regions expanded by moving the sides, and storing the dividing information as the terminal units in the external memory device.
REFERENCES:
patent: 4752887 (1988-06-01), Kuwahara
patent: 5483481 (1996-01-01), Hizume et al.
patent: 5757089 (1998-05-01), Ishizuka
patent: 6-291188 (1994-10-01), None
patent: 10-294377 (1998-11-01), None
Kodowaki, “Automatic Wiring System dor Semoconductor Integrated Circuit (English Translation)”, Japanese Patent No. 06291188, Oct. 1994, Japan Patent Office.
Lin Sun James
McGinn & Gibb PLLC
NEC Corporation
Smith Matthew
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