Method for distributing clock signals to flip-flop circuits

Details Method for distributing clock signals to flip-flop circuits Method for distributing clock signals to flip-flop circuits

2006-07-11

2006-07-11

Barnie, Rexford (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S094000, C326S095000, C326S096000, C326S097000, C326S098000, C716S030000, C716S030000, C713S400000, C713S401000

Reexamination Certificate

active

07075336

ABSTRACT:
A method for distributing clocks to flip-flop circuits which constitute a logic circuit includes obtaining a timing slack of a first minimum delay time with respect to a minimum delay constraint time and a timing slack of a first maximum delay time with respect to a maximum delay constraint time for a clock in an input path to a flip-flop circuit, obtaining a timing slack of a second minimum delay time with respect to a minimum delay constraint time and a timing slack of a second maximum delay time with respect to a maximum delay constraint time for a clock in an output path from all the flip-flop circuits which receive the clocks from a clock terminal directly and obtaining a delay value which maximizes a minimum value of each of the first and second minimum delay time and maximum delay time of timing slacks.

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