Computer graphics processing and selective visual display system – Computer graphics display memory system – Plural storage devices
Reexamination Certificate
2000-10-06
2004-09-28
Lao, Lun-Yi (Department: 2673)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Plural storage devices
C345S519000, C345S520000, C345S698000, C345S552000
Reexamination Certificate
active
06798419
ABSTRACT:
1. BACKGROUND OF THE INVENTION
The invention relates to a method for displaying data on a video display. More specifically, the invention relates to a method for displaying data on a video display controlled by a video controller subsystem having a high-speed memory and a low speed memory.
Many modern personal computers contain a relatively small number of electronic components. The motherboard components typically include a microprocessor, system memory, video memory, a video controller, and a chipset.
Video memory is a block of RAM in the video subsystem in which displayable data is stored. The video memory typically lies within the address space of the microprocessor. Thus, a program executing within the microprocessor can read from and write to video memory in the same way that is accesses system memory.
The video controller is a device that continually and repeatedly refreshes a video display by generating horizontal and vertical timing signals. The video controller also increments a video memory address counter at a rate that is synchronized with the timing signals. The video controller then reads data from the video memory using the address counter and decodes the data. Next, the video controller sends the decoded color and brightness signals along with the timing signals to the video display. This reading, decoding and sending cycle repeats between 60 and 78 times per second on conventional personal computers.
As a result of the synchronization discussed above, each bit or group of bits in the video memory specifies the color and brightness of a particular pixel on the video display. Thus, a bit can be said to correspond to a particular location on the video display.
As is well known by those skilled in the art, the chipset performs the function of interfacing the microprocessor to system memory and to system buses. In an effort to further reduce the component count and system cost, some modem chipset designs integrate the video controller and the chipset on a single device. This device will be referred to as an integrated chipset. The integrated chipset is made possible by the advancement of packaging technologies such as the high pin-count ball grid array (BGA) packages. The BGA packages allow a single device to incorporate all the required interfaces between the system memory and the microprocessor.
The inclusion of the video controller into the chipset may also eliminate the need for a separate video memory. However, if system memory is used to store video data, a reduction in performance occurs. This reduction in performance is due to the fact that both the video controller and microprocessor must share access to system memory. A personal computer with a state-of-the-art memory bus has a theoretical peak transfer rate of 264 MB/sec (Megabytes/sec). However, a 72 Hz video display system with a resolution of 1280×1024 pixels, each pixel being one of a possible 64 thousand colors, requires a video data bandwidth of approximately 260 MB/sec. Even a more moderate 72 Hz video display system with a resolution of 800×600 pixels, each pixel being one of a possible 64 thousand colors, requires a video data bandwidth of approximately 100 MB/sec. Thus, it is evident that the video data bandwidth is a significant portion of the total system memory bandwidth of a personal computer. As a result, the microprocessor must spend significant portions of its time waiting for access to system memory.
In addition, to the high pin-count packages, recent advances in semiconductor processing have reduced semiconductor geometries. Thus, space exists on the integrated chipset die for additional functionality.
2. SUMMARY OF THE INVENTION
The invention relates to a method and apparatus for displaying data on a video display that is controlled by a video controller. The video controller is coupled to a high-speed memory and a low-speed memory. The memories have separate data paths. The method consists of first receiving a video address corresponding to a location on the video display. Next, if a specified address bit is in a first state, then data is displayed from the high-speed memory. If the specified address bit is in a second state, then data is displayed from the low-speed memory. The specified address bit may be a high order address bit that is not utilized by a conventional VGA controller to transmit address information.
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Lao Lun-Yi
Micro)n Technology, Inc.
Trop Pruner & Hu P.C.
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