Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
1999-03-30
2001-03-27
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S127000, C257S778000
Reexamination Certificate
active
06207475
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to a method for dispensing underfill in a flip chip package formed of an IC chip and a substrate and devices formed by such method and more particularly, relates to a method for dispensing underfill in a flip chip package formed of an IC chip and a substrate either by a screen printing or a stencil printing technique, or by using dispensing nozzles for dispensing droplets of underfill onto a chip or substrate and devices formed by such methods.
BACKGROUND OF THE INVENTION
In the fabrication of modern semiconductor devices, the ever increasing device density and decreasing device dimensions demand more stringent requirements in the packaging or interconnecting techniques of the devices. In recent years, a flip-chip attachment method or a flip-chip direct chip attachment (DCA) method has been used in packaging integrated circuit chips. In the flip-chip attachment method, instead of attaching an integrated circuit lead frame in a package, an array of solder balls is formed on the surface of the die for the subsequent bonding to a printed circuit board or an interposer. The formation of the solder balls can be carried out by an evaporation method utilizing a solder material consisting mainly of tin and lead through a mask to produce the balls in a desired pattern. More recently, the techniques of eletrodeposition or printing have been used to mass produce solder balls in a flip-chip packaging process.
In the flip-chip attachment method, all the interconnections between a semiconductor chip and a printed circuit board (PCB) or an interposer can be formed simultaneously and therefore maximizing fabrication throughputs. For instance, in direct chip attachment, solder bumps or solder balls are used to connect a chip directly to a printed circuit board or an interposer. In a regular printed circuit board, the density of the interconnections is not formed high enough to match that normally found on a chip surface. In other words, the pitch between the bond pads formed on a chip is smaller than the pitch formed between interconnections on a printed circuit board. An interposer is therefore used to provide a transition and to accommodate the bond pads/interconnections which are spaced differently. An interposer board is frequently fabricated of the same material as that used in the printed circuit board, i.e., an epoxy-type polymeric material. When a high density interconnect printed circuit board is utilized in a flip-chip method for bonding to a semiconductor chip, the use of the interposer may not be necessary.
The use of organic substrates, or polymeric-base substrates, in printed circuit boards or interposers introduces a new source of problem for the flip-chip bonding of a silicon chip which is mostly inorganic to such substrates. The problem is the mismatch of coefficients of thermal expansion (CTE) between the printed circuit board and the silicon chip. The coefficient of thermal expansion for the printed circuit board material is at least five times that of the silicon material. The extreme mismatch in CTE's between the silicon chip and the organic substrate of the printed circuit board therefore subjects solder joints formed thereinbetween to extremely large thermal strains, which leads to premature failure of the solder connections.
One method proposed for alleviating such thermal strains is the introduction of an encapsulating layer between the silicon chip and the organic substrate. The encapsulating material, known as an underfill, which is typically a silica filled epoxy is used to fill the gap (or standoff) between the printed circuit board and the silicon chip. Since the silicon chip is normally covered, in a final fabrication step, by a polymer passivation/stress buffer layer such as a polyimide film, the underfill forms a bond between the polyimide layer on the chip and the organic substrate of the printed circuit board encapsulating the solder joints.
Referring initially to
FIG. 1
, wherein a flip-chip
10
bonded by a plurality of solder balls
12
and an underfill layer
14
is shown. The encapsulating material, or the underfill layer
14
, is typically a silica fill epoxy for filling the gap, or the standoff, between the printed circuit board
16
and the silicon chip
18
. As shown in
FIG. 1
, the underfill layer
14
forms a bond between a polyimide layer
20
, which is a passivation/stress buffer layer that covers the silicon chip
18
, and the printed circuit board
16
encapsulating the solder balls
12
.
While the introduction of the underfill layer between a silicon chip and an organic substrate for the printed circuit board has enhanced the thermal cycling resistance of a flip chip assembly, the dispensing of the underfill material in between a silicon chip and a substrate and filling the gap is a time consuming task. In one conventional method, as shown in FIGS.
2
A~
2
C, an underfill dispenser
22
is first used to dispense an underfill material
24
onto the top surface
26
of a substrate
28
. A layer
30
of the underfill material
24
is thus formed on the top surface
26
. A chip holder
32
, usually a vacuum holder, is then used to position an IC chip
34
which is pre-deposited with a plurality of solder balls
36
on a top surface
38
over the substrate
28
. The IC chip, or die
34
is then pressed onto the substrate
28
with the plurality of solder balls
36
connecting to corresponding electrical conductors (not shown) on the surface
26
of the substrate
28
. The assembly
40
for the flip chip is then placed in a reflow oven and heated to a temperature not less than the reflow temperature for the solder material utilized in the plurality of solder balls
36
. The reflow process further cures the underfill material
30
and improves its mechanical strength.
Several drawbacks are inherent in this technique, for instance, there is possibly an underfill material layer between the plurality of solder balls on the IC chip and the plurality of electrical conductors on the substrate. Since the underfill material is an insulating material, this affects the contact resistance formed between the joints. Secondly, in the process of pressing the IC die
34
onto the underfill material layer
30
, air entrapment in the underfill material
30
is inevitable. Trapped air bubbles in the underfill material layer
30
, or in the epoxy material layer
30
, affects the mechanical strength enhancement by the underfill material and furthermore, affects the adhesion formed between the underfill material and the IC die or the substrate.
In another conventional technique for dispensing underfill materials, as shown in FIGS.
3
A~
3
F, an underfill material is fed into the standoff between an IC die and a substrate by the capillary effect on the underfill liquid. As shown in
FIG. 3A
, a wafer
42
is first sectioned into individual dies
44
by a diamond saw
46
. The IC dies
44
are provided with a plurality of solder balls
48
on a top surface
50
of the dies. After all the dies
44
are severed from wafer
42
, they are placed in a holding tray
52
, as shown in FIG.
3
B. In the next step of the process, a vacuum head
54
is used to remove an IC die
44
from the tray
52
and to position the die over a substrate
56
. It is noted that a plurality of electrical conductors
58
, corresponding to the number and positions of the solder balls
48
are provided on a top surface
60
of the substrate
56
. It should be noted that the substrate
56
may be either a printed circuit board or an interposer. After the IC die
44
is mounted to substrate
56
by intimately contacting the solder balls
48
with the electrical conductors
58
, as shown in
FIG. 3D
, a solder reflow process is carried out to reflow the solder and to form a permanent bond between the IC die
44
and the substrate
56
. It should be noted that the plurality of electrical conductors
58
are not shown in
FIG. 3D
for simplicity reasons.
The flip chip package
62
is now ready for the underfill process in which an underf
Lin Shih Hsiung
Wang Hsing Seng
Bowers Charles
Industrial Technology Research Institute
Smoot Stephen W.
Tung & Associates
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