Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-04-19
2003-09-23
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06625785
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to methods for determining processing parameters of integrated circuits (“IC”s), and particularly to methods for determining variations in integrated circuit processing parameters and the cause thereof.
Analog ICs are specified by a set of performance metrics, such as gain, bandwidth, total harmonic distortion, slew rate and the like, which are measured during production and tested against specified limits, called performance specifications, to determine whether the ICs are good or bad. This process is known as specification testing. Analog ICs, in general, have many complex performance metrics that depend on a multitude of device parameters.
Parametric yield loss, that is, the failure of a significant portion of ICs manufactured to pass specification tests due to variations in process parameters, is often a problem in analog IC designs. Usually, a large number of designs are manufactured using the same manufacturing process and the dependencies of the performance of these designs on device parameters are often different. The tuning of the process to improve the yield for one design may adversely affect the yields for other designs. Process shifts over time can also cause a reduction in yield.
The dependencies of analog IC performance metrics on production process fluctuations are very complex and not known in closed form. The performance metrics of an analog IC depend on the values of a set of device parameters of the IC (Vt, Kn, number of transistors, resistivity, etc.). Yet, the ICs ordinarily comprise a large number of devices, such as transistors, resistors and capacitors whose nodes are not available for direct measurement to determine those device parameters.
Various techniques for diagnosing process fluctuations from measured device parameters have previously been disclosed in, for example, C. J. B. Spanos and S. W. Director, “Parameter Extraction for Statistical IC Process Characterization,” IEEE Transactions on Computer-Aided Design, Vol. 5, CAD-5, January 1986, pp. 66-78; G. Freeman, W. Lukaszek, J. Y. C. Pan, “MERLIN: A Device Diagnosis System based on Analytic Models,” IEEE Transactions on Semiconductor Manufacturing, Vol. 6, No. 4, November 1993, pp. 306-317; and M. Qu and M. A. Styblinski, “Parameter Extraction for Statistical IC Modeling Based on Recursive Inverse Approximation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 6, No. 11, November 1997, pp. 1250-1259. However, since device parameters can only be measured on a few test sites on a wafer, these procedures cannot be used to diagnose problems caused by variation of parameters between different chips on the same wafer. Also, the relationship between device parameters and the performance metrics of a circuit are often not known well enough to diagnose the cause of circuit performance variations in terms of variations in device parameters.
It has been shown previously that the device parameters which control a circuit's behavior can be computed from measurements made on the circuit, if the measurements satisfy certain diagnosability conditions. S. Cherubal and A. Chatterjee, “Parametric fault Diagnosis for Analog ICs Using Functional Mapping,” Proceedings, Design Automation and Test in Europe, 1999, pp. 195-200 (“Cherubal and Chatterjee”), and E. Liu, W. Kao, E. Felt and A. Sangiovanni-Vincentelli, “Analog testability analysis and Fault diagnosis using behavioral modeling,” Proceedings, IEEE Custom Integrated Circuits Conference, 1994, pp. 413-416. An efficient algorithm for the computation of device parameters has been disclosed in Cherubal and Chatterjee, supra.
Semiconductor ICs are manufactured in lots of wafers, which contain large numbers (typically thousands) of ICs. Each wafer contains a few sites which have special test structures which enable the measurement of device parameters (electrical test or “ET” measurements). If the ET parameters are within prescribed limits, specification tests are performed on the ICs on the wafer and the “good” ICs are diced, packaged and tested again against a full set of specifications. The limits on the ET measurements are usually set to be very wide, so that a wafer containing some good ICs is not rejected. Analog ICs often face yield problems wherein a set of the ICs on a wafer fails the specification tests, while the ET data is within limits.
Two typical yield problems are shown in FIG.
1
(
a
) and FIG.
1
(
b
), which illustrate possible histograms of performance metrics of ICs. In FIG.
1
(
a
) a shift in a process parameter causes yield loss (shaded region) while in FIG.
1
(
b
) a large variance in a performance metric causes loss in yield. These yield problems are often caused by the variation of device parameters across a wafer, that is, chip-to-chip variation in device parameters.
The IC manufacturing process may be modelled hierarchically, as shown in FIG.
2
. Every step in the manufacturing process is affected by a set of process disturbances, such as changes in diffusivity of dopants, oxide growth rates, and the like, which result in fluctuations in device parameters of ICs.
The device parameters in turn control the performance metrics of ICs, which determine yield. The process disturbances cause the device parameters vary from lot-to-lot, from wafer to wafer within a lot, and from IC to IC within a wafer. The lot-to-lot and wafer-to-wafer variations can be monitored by measuring the device parameters using the wafer test structures. However, in the current manufacturing methodology there is no way of directly monitoring the variation of device parameters across ICs on a wafer. This makes the diagnosis of yield problems caused by the variation of device parameters within a wafer extremely difficult.
SUMMARY OF THE INVENTION
The present invention solves the aforementioned problems and meets the aforementioned needs by estimating the device parameters of a given circuit from the output of the circuit stimulated with an input that is optimized for this purpose. Once the optimum test signal has been identified, a regression model is constructed to relate measured circuit performance metrics to the estimated device parameters. A non-linear cause-effect analysis is used to diagnose the process cause of the variation in device parameter values. This information can be used by process engineers to tune the manufacturing process to improve yield.
Accordingly, it is a principle object of the present invention to provide a novel and improved method for diagnosing process parameter variations from measurements in analog circuits.
It is another object of the present invention to provide a novel method for computing device parameters from circuit performance metrics in the presence of noise.
It is a further object of the present invention to provide a novel method for generating an optimum test signal for determining device parameters of an analog circuit based on performance metrics of an output signal generated in response to the optimum test signal.
It is yet another object of the present invention to optimize the number of device parameters of an analog integrated circuit that can be determined with a given degree of accuracy from circuit performance metrics.
It is yet a further object of the present invention to provide a novel method for determining the processing cause of variations in circuit performance metrics from their ideal.
The foregoing and other objects, features, and advantages of the invention will be more readily understood upon consideration of the following detailed description of the invention, taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5539652 (1996-07-01), Tegethoff
patent: 6212667 (2001-04-01), Geer et al.
patent: 2001/0010091 (2001-07-01), Noy
patent: 2002/0002698 (2002-01-01), Hekmatpour
patent: 2002/0133772 (2002-09-01), Voorakaranam et al.
Variyam et al, “Specification-driven test design for analog circuits”, IEEE, 1998.*
C.J.B. Spanos & S.W. Director, “Parameter Extraction for Statistical IC Process Character
Chatterjee Abhijit
Cherubal Sasikumar
Birdwell Janke & Durando, PLC
Bowers Brandon
Garbowski Leigh M.
Georgia Tech Research Corporation
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