Radiation imagery chemistry: process – composition – or product th – Imaging affecting physical property of radiation sensitive... – Making electrical device
Reexamination Certificate
2000-07-12
2002-04-30
Huff, Mark F. (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Imaging affecting physical property of radiation sensitive...
Making electrical device
C430S030000, C430S311000, C430S313000, C430S317000, C430S329000, C430S331000
Reexamination Certificate
active
06379870
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process for monitoring the quality of via or trench formation in the production of a semiconductor device. More particularly, the invention pertains to a process for detecting side wall oxidation of low dielectric constant materials during the formation of vias and/or trenches in dielectrics.
2. Description of the Related Art
It is common in the art of manufacturing semiconductors to form semiconductors comprising a low dielectric constant (low-k) material on a silicon based wafer substrate. The most commonly used low-k dielectrics are silicates, siloxanes, silsesquioxanes, and organic polymers, such as polyimides. Conventional manufacturing processes for semiconductors generally use known spin-on-glass (SOG) application techniques to deposit the dielectric material onto the substrate.
After the dielectric material is deposited onto substrate, it is typical to form vias or trenches in the dielectric material using etching techniques that are well known in the art. During these etching processes, it is not uncommon for a small amount of exposed low dielectric constant dielectric material on the via or trench side walls to be damaged due to unavoidable oxidation or erosion. This damage along the side walls of the vias and/or trenches will adversely affect the electrical properties of the semiconductor because it will increase via resistance and result in poor connections with metallic interconnects. This damage may also result in higher dielectric constants and interfere with the overall performance of the semiconductor.
U.S. Pat. No. 6,074,941 teaches a method for forming vias using a plasma etchant with a fixed ratio of hydrogen and another to gas treat an exposed SOG layer. Structures formed using SOG methods have been known to outgas or poison the vias or trenches during processing steps. The outgassing causes defects to form within the vias or trenches, often at the side walls. Such defects may lead to higher and varying resistances and lower product yields. In U.S. Pat. No. 5,883,014, a hydrogen plasma treatment is performed on via side walls in the production of inter-metal dielectric layers to prevent damage to the side walls from out-gassing. This treatment avoids the deleterious affects of damage to the vias, such as decreased electrical potential, and superior electrical properties are maintained. U.S. Pat. No. 5,371,047 discloses an integrated circuit in which a composite dielectric layer is formed comprising an organic dielectric material, such as a polyimide, and an etch resistant layer on the organic layer. The etch resistant layer protects the organic layer from defects resulting either from patterning of the organic layer through reactive ion etching, the etching of a metal pattern over the organic layer, or from damage due to metal polishing processes. Avoiding such damage to dielectric materials is essential in forming semiconductors having good performance.
The importance of avoiding damage to low dielectric constant materials to produce semiconductors having good performance is well known in the art. To combat this problem, it is first necessary to identify and quantify any damage arising during manufacturing. However, because of the microscopic size of the vias and trenches, presently known techniques have had difficulty in detecting faults on the side walls. For example, surface probing techniques such as secondary ion mass spectroscopy (SIMS), x-ray photoelectron spectroscopy (XPS) and thin film Fourier transform infrared spectroscopy (FTIR) do not have signal intensity capabilities or small enough spot size to analyze the side walls of vias or trenches. Other known damage detecting techniques include experiments done on blanket films exposing the dielectric surface to a flux of ions or radicals perpendicular to the surface. However, these techniques are ineffective to inspect side walls that are parallel to the flux, and do not give an accurate indication of the extent of side wall damage. Therefore, it is difficult for manufacturers of semiconductor devices to assess whether certain etching or ashing techniques are compatible with low-k materials, hindering their integration into devices.
The present invention provides a process by which such side wall defects can be inspected to allow manufacturers to determine whether improved etching or ashing techniques are necessary. In particular, after etching vias in a sample of low-k materials and stripping or ashing off any photoresist, the sample is then cleaved for cross-sectional analysis. This cleaved surface is then immersed into a solvent for a time sufficient to remove partially oxidized low-k material. The cross-section is then analyzed by scanning electron microscopy and a simple visual inspection of the cross sectioned via or trench will show the extent or depth of the damage. This process allows manufacturers to determine whether certain etching and/or ashing processes will damage low-k materials and determine the depth and extent of oxidation in vias and in trenches, and allow production of semiconductor products having a better performance.
SUMMARY OF THE INVENTION
The invention provides a process for determining the quality of side walls of vias and/or trenches formed through a dielectric coating comprising the steps of:
a) forming a dielectric coating on a substrate;
b) depositing a photoresist onto the dielectric coating;
c) imagewise patterning and developing the photoresist;
d) etching the dielectric coating to form a pattern of vias and/or trenches in the dielectric coating;
e) removing the remaining photoresist;
f) cleaving the substrate across at least one of the vias and/or trenches;
g) contacting the substrate with a solvent to thereby remove partially oxidized portions of the dielectric coating on side walls of the vias and/or trenches; and
h) inspecting the side walls of the vias and/or trenches for defects.
The invention also provides a process for determining the quality of side walls of vias and/or trenches formed through a dielectric coating comprising the steps of:
a) providing a dielectric coating on a substrate, which dielectric coating has vias and/or trenches formed therethrough;
b) cleaving the substrate across at least one of the vias and/or trenches;
c) contacting the substrate with a solvent to thereby remove partially oxidized portions of the dielectric coating on side walls of the vias and/or trenches; and
d) inspecting the side walls of the vias and/or trenches for defects.
REFERENCES:
patent: 4988877 (1991-01-01), Stokowksi et al.
patent: 5371047 (1994-12-01), Greco et al.
patent: 5413963 (1995-05-01), Yen et al.
patent: 5759273 (1998-06-01), Martini et al.
patent: 5851925 (1998-12-01), Beh et al.
patent: 5883014 (1999-03-01), Chen et al.
patent: 6074941 (2000-06-01), Hsieh et al.
patent: 6207583 (2001-03-01), Dunne et al.
patent: 59-39044 (1984-03-01), None
Barreca Nicole
Honeywell International , Inc.
Huff Mark F.
Roberts & Mercanti LLP
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